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e ? intel corporation 1996, 1997 april 1997 order number: 290550-002 n bridge between the pci bus and isa bus n pci and isa master/slave interface ? pci from 25 C33 mhz ? isa from 7.5C8.33 mhz ? 5 isa slots n fast ide interface ? supports pio and bus master ide ? supports up to mode 4 timings ? transfer rates to 22 mb/sec ? 8 x 32-bit buffer for bus master ide pci burst transfers ? separate master/slave ide mode support (piix3) n plug-n-play port for motherboard devices ? 2 steerable dma channels (piix only) ? fast dma with 4-byte buffer (piix only) ? 2 steerable interrupts lines on the piix and 1 steerable interrupt line on the piix3 ? 1 programmable chip select n steerable pci interrupts for pci device plug- n-play n pci specification revision 2.1 compliant (piix3) n functionality of one 82c54 timer ? system timer; refresh request; speaker tone output n two 82c59 interrupt controller functions ? 14 interrupts supported ? independently programmable for edge/level sensitivity n enhanced dma functions ? two 8237 dma controllers ? fast type f dma ? compatible dma transfers ? 7 independently programmable channels n x-bus peripheral support ? chip select decode ? controls lower x-bus data byte transceiver n i/o advanced programmable interrupt controller (ioapic) support (piix3) n universal serial bus (usb) host controller (piix3) ? compatible with universal host controller interface (uhci) ? contains root hub with 2 usb ports n system power management (intel smm support) ? programmable system management interrupt (smi)hardware events, software events, extsmi# ? programmable cpu clock control (stpclk#) ? fast on/off mode n non-maskable interrupts (nmi) ? pci system error reporting n nand tree for board-level ate testing n 208-pin qfp the 82371fb (piix) and 82371sb (piix3) pci isa ide xcelerators are multi-function pci devices implementing a pci-to-isa bridge function and an pci ide function. in addition, the piix3 implements a universal serial bus host/hub function. as a pci-to-isa bridge, the piix/piix3 integrates many common i/o functions found in isa-based pc systems a seven-channel dma controller, two 82c59 interrupt controllers, an 8254 timer/counter, and power management support. in addition to compatible transfers, each dma channel supports type f transfers. chip select decoding is provided for bios, real time clock, and keyboard controller. edge/level interrupts and interrupt steering are supported for pci plug and play compatibility. the piix/piix3 supports two ide connectors for up to four ide devices providing an interface for ide hard disks and cd roms. the piix/piix3 provides motherboard plug and play compatibility. piix implements two steerable dma channels (including type f transfers) and up to two steerable interrupt lines. piix3 implements one steerable interrupt line. the interrupt lines can be routed to any of the available isa interrupts. both piix/piix3 implement a programmable chip select. piix3 contains a universal serial bus (usb) host controller that is uhci compatible. the host controllers root hub has two programmable usb ports. piix3 also provides support for an external ioapic. this document describes the piix3 component. unshaded areas describe the 82371fb piix. shaded areas, like this one, describe the piix3 operations that differ from the 82371fb piix. 82371fb (piix) and 82371sb (piix3) pci isa ide xcelerator
82371fb (piix) and 82371sb (piix3) e 2 usbp1 usbp0 pci bus interface isa bus interface mother board interface interrupt timers/ counters dma pciclk ad[31:0] c/be[3:0]# frame# irdy# trdy# stop# devsel# serr# par idsel mirq1 mdrq[1:0] mdak[1:0]# intr nmi irq(15,14,11:9,7:3,1) dack[7:5,3:0]# tc refresh# sd[15:0] la23/cs1s iocs16# memcs16# dd12/sbhe# memr# memw# aen iochrdy iochk# sysclk bale ior# iow# smemr# smemw# zerows# blkdia.drw spkr ferr# ignne# x-bus support logic osc irq12/m irq8# test testin# or apicreq# pirq[a:d]# smi# stpclk# extsmi# system power mgmt phold# pholda# system reset pwrok cpurst pcirst# or apicack# rstdrv init ide interface sa[7:0] dd[11:0]/sa[19:8] m u x la22/cs3s la21/cs1p la20/cs3p la19:17]/da[2:0] dior# diow# ddrq[1:0] ddak[1:0]# iordy soe# sdir dd15/pcs# m u x xdir# xoe# rtcale bioscs# rtccs# kbcs# dd13 dreq[7:5,3:0] i/o apic support logic m u x dd14 pcirst# testin# dd14 or apiccs# universial serial interface usbclk piix only (not on piix3) mirq0 piix3 only (not on piix) piix3 only (not on piix) note: 1. ioapic signals are multiplexed with signals from the system reset, test, and ide interface blocks 2. pirqd# is an input on the piix and bi-directional on piix3. piix/piix3 simplified block diagram
e 82371fb (piix) and 82371sb (piix3) 3 contents page revision history...................................................................................................................................... 7 1.0. signal description .......................................................................................................................... 9 1.1. pci interface signals ........................................................................................................................... 9 1.2. motherboard i/o device interface signals .......................................................................................... 10 1.3. ide interface signals ......................................................................................................................... 11 1.4. isa interface signals.......................................................................................................................... 13 1.5. dma signals ...................................................................................................................................... 15 1.6. timer/counter signals........................................................................................................................ 15 1.7. interrupt controller signals................................................................................................................. 16 1.8. system power management (smm) signals ...................................................................................... 16 1.9. x-bus signals .................................................................................................................................... 17 1.10. apic bus signals (piix3 only) ........................................................................................................ 18 1.11. universal serial bus signals (piix3 only) ........................................................................................ 19 1.12. system reset signals ...................................................................................................................... 19 1.13. test signals ..................................................................................................................................... 20 1.14. power and ground signals............................................................................................................... 20 1.15. signal state during reset ................................................................................................................ 21 2.0. register description ................................................................................................................... 22 2.1. register access ................................................................................................................................. 22 2.2. pci configuration registers pci to isa bridge (function 0)........................................................... 31 2.2.1. vidvendor identification register (function 0)........................................................ 31 2.2.2. diddevice identification register (function 0) ......................................................... 31 2.2.3. pcicmdcommand register (function 0) ......................................................................... 31 2.2.4. pcistspci device status register (function 0) .......................................................... 32 2.2.5. ridrevision identification register (function 0)...................................................... 33 2.2.6. classc ? class code register (function 0)..................................................................... 33 2.2.7. hedtheader type register (function 0) ....................................................................... 33 2.2.8. iortisa i/o recovery timer register (function 0) ..................................................... 33 2.2.9. xbcsx-bus chip select register (function 0) ............................................................. 34 2.2.10. pirqrc[a:d]pirqx route control registers (function 0)...................................... 36 2.2.11. tomtop of memory register (function 0).................................................................. 36 2.2.12. mstatmiscellaneous status register (function 0)............................................... 37 2.2.13. mbirq[1:0]motherboard device irq route control registers (function 0) .. 39 2.2.14. mbdma[1:0]motherboard device dma control registers (function 0) ............ 40 2.2.15. pcscprogrammable chip select control register (function 0) ..................... 40 2.2.16. apicbaseapic base address relocation register (function 0) (piix3 only) ..... 41 2.2.17. dlcdeterministic latency control register (function 0) (piix3 only) ............. 42 2.2.18. smicntlsmi control register (function 0)................................................................ 43
82371fb (piix) and 82371sb (piix3) e 4 2.2.19. smien smi enable register (function 0) ....................................................................... 43 2.2.20. seesystem event enable register (function 0) ...................................................... 44 2.2.21. ftmrfast off timer register (function 0)................................................................. 45 2.2.22. smireqsmi request register (function 0) ................................................................. 45 2.2.23. ctltmrclock scale stpclk# low timer (function 0) .............................................. 46 2.2.24. cthtmrclock scale stpclk# high timer (function 0)............................................. 47 2.3. pci configuration registerside interface (function 1) ................................................................... 47 2.3.1. vidvendor identification register (function 1) ........................................................................ 47 2.3.2. diddevice identification register (function 1) ......................................................... 47 2.3.3. pcicmdcommand register (function 1) ......................................................................... 48 2.3.4. pcistspci device status register (function 1) .......................................................... 48 2.3.5. ridrevision identification register (function 1)...................................................... 49 2.3.6. classc ? class code register (function 1)..................................................................... 49 2.3.7. mltmaster latency timer register (function 1) ...................................................... 49 2.3.8. hedtheader type register (function 1) ....................................................................... 50 2.3.9. bmibabus master interface base address register (function 1) ...................... 50 2.3.10. idetimide timing register (function 1) ........................................................................ 51 2.3.11. sidetimslave ide timing register (function 1) (piix3 only) ..................................... 52 2.4. pci configuration registers ? universal serial bus (function 2) (piix3 only).................................... 53 2.4.1. vidvendor identification register (function 2) (piix3)............................................ 53 2.4.2. did ? device identification register (function 2) (piix3) ............................................. 54 2.4.3. pcicmd ? command register (function 2) (piix3) ............................................................. 54 2.4.4. ds ? device status register (function 2) (piix3)............................................................. 55 2.4.5. rid ? revision identification register (function 2) (piix3).......................................... 55 2.4.6. classc ? class code register (function 2) (piix3)......................................................... 56 2.4.7. mlt ? master latency timer register (function 2) (piix3) .......................................... 56 2.4.8. hedt ? header type register (function 2) (piix3) ........................................................... 57 2.4.9. baseadd ? i/o space base address (function 2) (piix3) ................................................ 57 2.4.10. il ? interrupt line register (function 2) (piix3)......................................................................... 57 2.4.11. intrp ? interrupt pin (function 2) (piix3) ......................................................................... 58 2.4.12. sbrnum ? serial bus release number (function 2) (piix3) ......................................... 58 2.4.13. mstat ? miscellaneous status register (function 2) (piix3)................................... 58 2.4.14. legsup ? legacy support register (function 2) (piix3) ........................................ 59 2.5. isa-compatible registers .................................................................................................................. 61 2.5.1. dma registers....................................................................................................................... 61 2.5.1.1. dcomdma command register........................................................................................ 61 2.5.1.2. dcmdma channel mode register.................................................................................... 61 2.5.1.3. drdma request register................................................................................................. 62 2.5.1.4. mask registerwrite single mask bit ................................................................................. 63 2.5.1.5. mask registerwrite all mask bits...................................................................................... 63 2.5.1.6. dsdma status register.................................................................................................... 64 2.5.1.7. dma base and current address registers (8237 compatible segment).............................. 64 2.5.1.8. dma base and current byte/word count registers (compatible segment) ........................ 65
e 82371fb (piix) and 82371sb (piix3) 5 2.5.1.9. dma memory low page registers ....................................................................................... 65 2.5.1.10. dma clear byte pointer register........................................................................................ 66 2.5.1.11. dmc dma master clear register..................................................................................... 66 2.5.1.12. dclmdma clear mask register ..................................................................................... 66 2.5.2. timer/counter register description .......................................................................... 66 2.5.2.1. tcwtimer control word register..................................................................................... 66 2.5.2.2. interval timer status byte format register .......................................................................... 68 2.5.2.3. counter access ports register ............................................................................................. 69 2.5.3. interrupt controller registers ................................................................................. 69 2.5.3.1. icw1initialization command word 1 register................................................................... 70 2.5.3.2. icw2initialization command word 2 register................................................................... 70 2.5.3.3. icw3initialization command word 3 register................................................................... 71 2.5.3.4. icw3initialization command word 3 register................................................................... 71 2.5.3.5. icw4initialization command word 4 register................................................................... 71 2.5.3.6. ocw1operational control word 1 register ...................................................................... 72 2.5.3.7. ocw2operational control word 2 register ...................................................................... 72 2.5.3.8. ocw3operational control word 3 register ...................................................................... 73 2.5.3.9. elcr1edge/level triggered register............................................................................... 74 2.5.3.10. elcr2edge/level triggered register............................................................................. 74 2.5.4. x-bus, coprocessor, and reset registers ................................................................. 75 2.5.4.1. reset x-bus irq12 and irq1 register................................................................................ 75 2.5.4.2. coprocessor error register .................................................................................................. 75 2.5.4.3. rcreset control register ................................................................................................. 75 2.5.5. nmi registers ........................................................................................................................ 76 2.5.5.1. nmiscnmi status and control register ........................................................................... 76 2.5.5.2. nmi enable and real-time clock address register............................................................. 77 2.6. system power management registers .............................................................................................. 77 2.6.1. apmcadvanced power management control port ............................................. 77 2.6.2. apmsadvanced power management status port ................................................ 78 2.7. pci bus master ide registers.......................................................................................................... 78 2.7.1. bmicombus master ide command register ............................................................. 78 2.7.2. bmistabus master ide status register ................................................................... 79 2.7.3. bmidtpbus master ide descriptor table pointer register ............................. 80 2.8. usb i/o registers.............................................................................................................................. 80 2.8.1. usbcmd ? usb command register........................................................................................... 80 2.8.2. usbsts ? usb status register.................................................................................................. 82 2.8.3. usbintr ? usb interrupt enable register ................................................................................. 83 2.8.4. frnum ? frame number register.............................................................................................. 83 2.8.5. flbaseadd ? frame list base address register...................................................................... 84 2.8.6. start of frame (sof) modify register ........................................................................................ 84 2.8.7. portsc ? port status and control register ............................................................................... 85 3.0. functional description .............................................................................................................. 89
82371fb (piix) and 82371sb (piix3) e 6 3.1. memory and i/o address map ........................................................................................................... 89 3.1.1. i/o accesses ............................................................................................................................... 89 3.1.2. memory address map ................................................................................................................. 89 3.1.3. bios memory........................................................................................................................... 90 3.2. pci interface ...................................................................................................................................... 90 3.2.1. transaction termination ................................................................................................. 90 3.2.2. parity support ..................................................................................................................... 91 3.2.3. pci arbitration ..................................................................................................................... 91 3.3. isa interface ...................................................................................................................................... 92 3.4. dma controller................................................................................................................................... 93 3.4.1. type f timing .......................................................................................................................... 94 3.4.2. isa refresh cycles ............................................................................................................. 94 3.5. pci local bus ide ............................................................................................................................. 95 3.5.1. ata register block decode ............................................................................................. 96 3.5.2. enhanced timing modes ..................................................................................................... 97 3.5.2.1. back-to-back pio ide transactions.................................................................................... 98 3.5.2.2. iordy masking .................................................................................................................... 98 3.5.2.3. pio 32 bit ide data port mode ............................................................................................ 98 3.5.3. bus master function.......................................................................................................... 98 3.6. universal serial bus host controller (piix3 only) ............................................................................. 100 3.7. interval timer ................................................................................................................................... 102 3.8. interrupt controller ........................................................................................................................... 103 3.8.1. programming the icws/ocws ......................................................................................... 104 3.8.2. edge and level triggered mode .................................................................................. 104 3.8.3. interrupt steering........................................................................................................... 104 3.9. stand-alone ioapic support (piix3) ............................................................................................... 105 3.10. intr signaling with pentium? processor local apic in virtual wire mode ................................... 106 3.11. x-bus peripheral support............................................................................................................... 107 3.12. power management ....................................................................................................................... 108 3.12.1. smm mode ............................................................................................................................ 109 3.12.2. smi sources ....................................................................................................................... 109 3.12.3. clock control.................................................................................................................. 110 3.13. reset support ................................................................................................................................ 110 3.13.1. hardware strapping options ..................................................................................... 111 4.0. pinout and package information .......................................................................................... 112 4.1. pinout............................................................................................................................................... 112 4.2. package dimensions ................................................................................................................ 117 5.0. testability (piix/piix3) .................................................................................................................. 118 5.1. test mode description ..................................................................................................................... 118 5.2. nand tree mode............................................................................................................................. 118 5.3. tri-state mode.................................................................................................................................. 122
e 82371fb (piix) and 82371sb (piix3) 7 revision history revision date version description may 1996 -001 initial release april 1997 -002 included information from specification update information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by the sale of intel products. except as provided in intels terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel retains the right to make changes to specifications and product descriptions at any time, without notice. the intel 82371fb and 82371sb may contain design defects or errors known as errata. which may cause the products to deviate from published specifications. such errata are not covered by intels warranty. current characterized errata are available in intel 430fx tsc/tdp/piix specification update (order#297733)and intel 82371sb (piix3) pci isa ide xcelerator specification update (order#297658). third-party brands and names are the property of their respective owners.
82371fb (piix) and 82371sb (piix3) e 8
e 82371fb (piix) and 82371sb (piix3) 9 1.0. signal description this section contains a detailed description of each signal. the signals are arranged in functional groups according to their interface. note that the '#' symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when '#' is not present after the signal name, the signal is asserted when at the high voltage level. the terms assertion and negation are used extensively. this is done to avoid confusion when working with a mixture of 'active-low' and 'active-high' signals. the term assert , or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. the term negate , or negation indicates that a signal is inactive. note that certain signal pins provide two separate functions. at the system level, these pins drive other signals with different functions through external buffers or transceivers. these pins have two different signal names depending on the function. these signal names have been noted in the signal description tables, with the signal whose function is being described in bold font. (for example, la23/ cs1s is in the section describing cs1s and la23 /cs1s is in the section describing la23). the following notations are used to describe the signal type. i input is a standard input-only signal. o totem pole output is a standard active driver. i/o input/output is a bi-directional, tri-state signal. od open drain allows multiple devices to share as a wire-or. st schmitt trigger input. t/s tri-state is a bi-directional, tri-state input/output pin. s/t/s sustained tri-state is an active low tri-state signal owned and driven by one and only one agent at a time. the agent that drives a s/t/s pin low must drive it high for at least one clock before letting it float. a new agent can not start driving a s/t/s signal any sooner than one clock after the previous owner tri- states it. an external pull-up is required to sustain the inactive state until another agent drives it and must be provided by the central resource. 1.1. pci interface signals signal name type description pciclk i pci clock: pciclk provides timing for all transactions on the pci bus. all other pci signals are sampled on the rising edge of pciclk, and all timing parameters are defined with respect to this edge. pci frequencies of 25 C33 mhz are supported. ad[31:0] i/o pci address/data: the standard pci address and data lines. the address is driven with frame# assertion and data is driven or received in following clocks c/be[3:0]# i/o bus command and byte enables: the command is driven with frame# assertion. byte enables corresponding to supplied or requested data is driven on following clocks. frame# i/o (s/t/s) frame: assertion indicates the address phase of a pci transfer. negation indicates that one more data transfer is desired by the cycle initiator.
82371fb (piix) and 82371sb (piix3) e 10 signal name type description trdy# i/o (s/t/s) target ready: asserted when the target is ready for a data transfer. irdy# i/o (s/t/s) initiator ready: asserted when the initiator is ready for a data transfer. stop# i/o (s/t/s) stop: asserted by the target to request the master to stop the current transaction. idsel i initialization device select: idsel is used as a chip select during configuration read and write transactions. devsel# i/o (s/t/s) device select: the piix/piix3 asserts devsel# to claim a pci transaction through positive or subtractive decoding. par o calculated parity signal: par is "even" parity and is calculated on 36 bits ad[31:0] plus c/be[3:0]#. serr# i system error: serr# can be pulsed active by any pci device that detects a system error condition. upon sampling serr# active, the piix/piix3 can be programmed to generate a non-maskable interrupt (nmi) to the cpu. phold# o pci hold: the piix/piix3 asserts this signal to request the pci bus. the piix3 implements the passive release mechanism by toggling phold# inactive for one pciclk. phlda# i pci hold acknowledge: this signal is asserted to grant the pci bus to the piix/piix3. 1.2. motherboard i/o device interface signals signal name type description mdrq[1:0] (piix only) i motherboard device dma request: these signals can be connected internally to any of dreq[3:0,7:5]. each pair of request/ acknowledge signals is controlled by a separate register. each signal can be configured as steerable interrupts for motherboard devices. mdak[1:0]# (piix only) o motherboard device dma acknowledge: these signals can be connected internally to any of dack[3:0,7:5]. each pair of request/ acknowledge signals is controlled by a separate register. each signal can be configured as steerable interrupts for motherboard devices.
e 82371fb (piix) and 82371sb (piix3) 11 signal name type description mirq0/irq0 (piix3 only) mirq[1:0] (piix only) i/o i motherboard device interrupt request : the mirqx signals can be internally connected to interrupts irq[15,14,12:9,7:3]. each mirqx line has a separate route control register. if mirqx and pirqx# are steered to the same isa interrupt, the device connected to the mirqx should produce active high, level interrupts. the mirq0/irq0 signal has two functions (for piix3 only), depending on the programming of the irq0 enable bit (mirq0 register). in the systems that include the piix3 and ioapic, the mirq0/irq0 pin will function as the irq0 output and should be connected to the intin2 input of the ioapic. the interrupt from the secondary ide channel should be connected to the irq15 input on piix3 and to the intin15 input on the ioapic. in the systems that include the piix3 only, the interrupt from the secondary ide channel should be connected to the mirq0/irq0 input. if an mirq line is steered to a given irq input to the internal 8259, the corresponding isa irq is masked, unless the route control register is programmed to allow the interrupts to be shared. this should only be done if the device connected to the mirq line and the device connected to the isa irq line both produce active high, level interrupts. mirq0 can be configured as an output to connect the internal irq0 signal to an external io-apic. 1.3. ide interface signals signal name type description dd[15:0] / pcs#, sbhe#, sa[19:8] apiccs# (piix3) i/o o i/o i/o o disk data : these signals directly drive the corresponding signals on up to two ide connectors (primary and secondary). in addition, these signals are buffered (using 2xals245's on the motherboard) to produce the sa[19:8], pcs#, and sbhe# signals (see separate descriptions). for the piix3, dd14 is buffered to produce apiccs# dior# o disk i/o read : this signal directly drives the corresponding signal on up to two ide connectors (primary and secondary). diow# o disk i/o write : this signal directly drives the corresponding signal on up to two ide connectors (primary and secondary). ddrq[1:0] i disk dma request : these input signals are directly driven from the drq signals on the primary (ddrq0) and secondary (ddrq1) ide connectors. they are used in conjunction with the pci bus master ide function and are not associated with any isa-compatible dma channel. ddak[1:0]# o disk dma acknowledge : these signals directly drive the dak# signals on the primary (ddak0# ) and secondary (ddak1#) ide connectors. these signals are used in conjunction with the pci bus master ide function and are not associated with any isa-compatible dma channel.
82371fb (piix) and 82371sb (piix3) e 12 signal name type description iordy i io channel ready : this input signal is directly driven by the corresponding signal on up to two ide connectors (primary and secondary). soe# o system address transceiver output enable : this signal controls the output enables of the '245 transceivers that interface the dd[15:0] signals to the sa[19:8], sbhe#, pcs# and apiccs# (piix3 only) signals. sdir o system address transceiver direction : this signal controls the direction of the '245 transceivers that interface the dd[15:0] signals to the sa[19:8], sbhe#, pcis, and apiccs# (piix3 only), signals. default condition is high (transmit). when an isa bus master is granted use of the bus, the transceivers are turned around to drive the isa address [19:8] on dd[15:3]. the address can then be latched by the piix/piix3. in this case, the sdir signal is low (receive). the soe# and sdir signals taken together as a group can assume one of three states: soe# sdir state 0 1 pci to isa transaction 1 1 pci to ide 0 0 isa bus master signals buffered from la[23:17] these signals are buffered from the la[23:17] lines by an als244 tri-state buffer. the output enable of this buffer is tied asserted. these signals are set up with respect to the ide command strobes (dior# and iow#) and are valid throughout i/o transactions targeting the ata register block(s). signal name type description la23/ cs1s i/o chip select: cs1s is for the ata command register block and corresponds to the inverted cs1fx# on the secondary ide connector. cs1s is inverted externally (see pci local bus ide section). la22/ cs3s i/o chip select: cs3s is for the ata control register block and corresponds to the inverted cs3fx# on the secondary ide connector. cs3s is inverted externally (see pci local bus ide section). la21/ cs1p i/o chip select: cs1p is for the ata command register block and corresponds to the inverted cs1fx# on the primary ide connector. cs1p is inverted externally (see pci local bus ide section). la20/ cs3p i/o chip select: cs3p is for the ata control register block and corresponds to the inverted cs3fx# on the primary ide connector. cs3p is inverted externally (see pci local bus ide section). la[19:17] da[2:0] i/o disk address: da[2:0] are used to indicate which byte in either the ata command block or control block is being addressed.
e 82371fb (piix) and 82371sb (piix3) 13 1.4. isa interface signals signal name type description bale o bus address latch enable: bale is an active high signal asserted by the piix/piix3 to indicate that the address (sa[19:0], la[23:17]) and sbhe# signal lines are valid. aen o address enable: aen is asserted during dma cycles to prevent i/o slaves from misinterpreting dma cycles as valid i/o cycles. this signal is also driven high during piix/piix3 initiated refresh cycles. for the piix, when tc is sampled low on the assertion of pwork (external dma mode), the piix tri-states this signal. sysclk o isa system clock: sysclk is the reference clock for the isa bus and drives the bus directly. sysclk is generated by dividing pciclk by 3 or 4. the sysclk frequencies supported are 7.5 mhz and 8.33 mhz. sysclk is a divided down version of pciclk. hardware strapping option sysclk is tri-stated when pwrok is negated. the value of sysclk is sampled on the assertion of pwrok: if sampled high, the isa clock divisor is 3 (for 25 mhz pci). if sampled low, the divisor is 4 (for 30 and 33 mhz pci). iochrdy i/o i/o channel ready: resources on the isa bus negate iochrdy to indicate that additional time (wait states) is required to complete the cycle. this signal is normally high on the isa bus. iochrdy is an input when the piix/piix3 owns the isa bus and the cpu or a pci agent is accessing an isa slave or during dma transfers. iochrdy is output when an external isa bus master owns the isa bus and is accessing dram or a piix/piix3 register. iocs16# i 16-bit i/o chip select: this signal is driven by i/o devices on the isa bus to indicate that they support 16-bit i/o bus cycles. iochk# i i/o channel check: iochk# can be driven by any resource on the isa bus. when asserted, it indicates that a parity or an uncorrectable error has occurred for a device or memory on the isa bus. if enabled, a nmi is generated to the cpu. ior# i/o i/o read: ior# is the command to an isa i/o slave device that the slave may drive data on to the isa data bus (sd[15:0]). iow# i/o i/o write: iow# is the command to an isa i/o slave device that the slave may latch data from the isa data bus (sd[15:0]). la[23:17]/ cs1s cs3s cs1p cs3p da[2:0] i/o / o o o o o unlatched address: the la[23:17] address lines are bi-directional. these address lines allow accesses to physical memory on the isa bus up to 16 mbytes. the la[23:17] are also used to drive the ide interface chip selects and address lines via an external als244 buffer. see the ide interface signal descriptions.
82371fb (piix) and 82371sb (piix3) e 14 signal name type description sa[7:0], sa[19:8]/ dd[11:0] i/o i/o i/o system address bus: these bi-directional address lines define the selection with the granularity of one byte within the one-mbyte section of memory defined by the la[23:17] address lines. the address lines sa[19:17] that are coincident with la[19:17] are defined to have the same values as la[19:17] for all memory cycles. for i/o accesses, only sa[15:0] are used. sbhe#/ dd12 i/o i/o system byte high enable: sbhe# indicates, when asserted, that a byte is being transferred on the upper byte (sd[15:8]) of the data bus. sbhe# is negated during refresh cycles. memcs16# od memory chip select 16: memcs16# is a decode of la[23:17] without any qualification of the command signal lines. isa slaves that are 16-bit memory devices drive this signal low. the piix/piix3 drives this signal low during isa master to dram cycles. memr# i/o memory read: memr# is the command to a memory slave that it may drive data onto the isa data bus. this signal is also driven by the piix/piix3 during refresh cycles. memw# i/o memory write: memw# is the command to a memory slave that it may latch data from the isa data bus. smemr# o standard memory read: the piix/piix3 asserts smemr# to request an isa memory slave to drive data onto the data lines. if the access is below 1 mbyte (00000000 C000fffffh) during dma compatible, piix/piix3 master, or isa master cycles, the piix/piix3 asserts smemr#. smemr# is a delayed version of memr#. smemw# o standard memory write: the piix/piix3 asserts smemw# to request an isa memory slave to accept data from the data lines. if the access is below 1 mbyte (00000000C000fffffh) during dma compatible, piix/piix3 master, or isa master cycles, the piix/piix3 asserts smemw#. smemw# is a delayed version of memw#. zerows# i zero wait-states: an isa slave asserts zerows# after its address and command signals have been decoded to indicate that the current cycle can be shortened. a 16-bit isa memory cycle can be reduced to two sysclks. an 8-bit memory or i/o cycle can be reduced to three sysclks. zerows# has no effect during 16-bit i/o cycles. sd[15:0] i/o system data: sd[15:0] provide the 16-bit data path for devices residing on the isa bus. sd[15:8] correspond to the high order byte and sd[7:0] correspond to the low order byte. sd[15:0] are undefined during refresh.
e 82371fb (piix) and 82371sb (piix3) 15 1.5. dma signals signal name type description dreq [7:5,3:0] i dma request: the dreq lines are used to request dma service from the piix/piix3 's dma controller or for a 16-bit master to gain control of the isa expansion bus. the active level (high or low) is programmed via the dma command register. the request must remain active until the appropriate dackx# signal is asserted. dack [7:5,3:0]# o dma acknowledge: the dack output lines indicate that a request for dma service has been granted by the piix/piix3 or that a 16-bit master has been granted the bus. the active level (high or low) is programmed via the dma command register. these lines should be used to decode the dma slave device with the ior# or iow# line to indicate selection. if used to signal acceptance of a bus master request, this signal indicates when it is legal to assert master#. for the piix, when tc is sampled low on the assertion of pwork (external dma mode), the piix tri-states these signals. this mode is not available on piix3. tc o terminal count: the piix/piix3 asserts tc to dma slaves as a terminal count indicator. when all the dma channels are not in use, tc is negated (low). hardware strapping option (piix only) this strapping option selects between the internal isa dma mode and external dma mode. when tc is sampled high on the assertion of pwrok (isa dma mode), the piix drives the aen, tc, and dack#[7:5, 3:0] normally. when tc is sampled low on the assertion of pwrok (external dma mode), the piix tri-states the aen, tc, and dack[7:5, 3:0]# signals, and also forwards pci masters i/o accesses to location 0000h to isa. tc has an internal pull-up resistor. to tie tc low, an external 1 k w pull-down resistor should be used. for the piix3, this signal should not be pulled down. refresh# i/o refresh: as an output, refresh# indicates when a refresh cycle is in progress. it should be used to enable the sa[7:0] address to the row address inputs of all banks of dynamic memory on the isa bus. thus, when memr# is asserted, the entire expansion bus dynamic memory is refreshed. memory slaves must not drive any data onto the bus during refresh. as an output, this signal is driven directly onto the isa bus. this signal is an output only when the piix/piix3 dma refresh controller is a master on the bus responding to an internally generated request for refresh. as an input, refresh# is driven by 16-bit isa bus masters to initiate refresh cycles. 1.6. timer/counter signals signal name type description spkr o speaker drive: the spkr signal is the output of counter 2. osc i oscillator: osc is the 14.31818 mhz isa clock signal. it is used by the internal 8254 timer.
82371fb (piix) and 82371sb (piix3) e 16 1.7. interrupt controller signals signal name type description irq[15,14, 11:9, 7:3,1] i interrupt request: the irq signals provide both system board components and isa bus i/o devices with a mechanism for asynchronously interrupting the cpu. the assertion mode of these inputs depends on the programming of the two elcr registers. the irq14 signal must be used by the bus master ide interface function to signal interrupts on the primary ide channel. irq8# i interrupt request eight signal: irq8# is always an active low edge triggered interrupt input (i.e., this interrupt can not be modified by software). upon pcirst#, irq8# is placed in active low edge sensitive mode. irq12/m i interrupt request/mouse interrupt: in addition to providing the standard interrupt function (see irq[15,14,11:9,7:3,1] signal description), this pin can be programmed (via x-bus chip select register) to provide a mouse interrupt function. pirq[d:a]# i i/o for pirqd# (piix3 only) programmable interrupt request: the pirqx# signals can be shared with interrupts irq[15,14,12:9,7:3] as described in the interrupt steering section. each pirqx# line has a separate route control register. these signals require external pull-up resisters. for the piix3, the usb interrupt is output on pirqd#. intr od cpu interrupt: intr is driven by the piix/piix3 to signal the cpu that an interrupt request is pending and needs to be serviced. the interrupt controller must be programmed following pcirst# to ensure that intr is at a known state. nmi od non-maskable interrupt: nmi is used to force a non-maskable interrupt to the cpu. the piix/piix3 generates an nmi when either serr# or iochk# is asserted, depending on how the nmi status and control register is programmed. 1.8. system power management (smm) signals signal name type description smi# od system management interrupt: smi# is an active low synchronous output that is asserted by the piix/piix3 in response to one of many enabled hardware or software events. stpclk# od stop clock: stpclk# is an active low synchronous output that is asserted by the piix/piix3 in response to one of many hardware or software events. stpclk# connects directly to the cpu and is synchronous to pciclk. extsmi# i external system management interrupt: extsmi# is a falling edge triggered input to the piix/piix3 indicating that an external device is requesting the system to enter smm mode. this signal contains a weak internal pullup.
e 82371fb (piix) and 82371sb (piix3) 17 1.9. x-bus signals signal name type description xdir# o x-bus direction: xdir# is tied directly to the direction control of a 74f245 that buffers the x-bus data (xd[7:0]). xdir# is asserted for all i/o read cycles, regardless if the accesses are to a piix/piix3 supported device. xdir# is only asserted for memory cycles if bios sapce (piix and piix3) or apic space (piix3 only) has been decoded. for pci master inititated read cycles, xdir# is asserted from the falling edge of either ior# or memr# (from memr# only if bios space (piix and piix3) or apic (piix3 only) space has been decoded), depending on the cycle type. for isa master-initiated read cycles, xdir# is asserted from the falling edge of either ior# or memr# (from memr# only if bios space has been decoded), depending on the cycle type. when the rising edge of ior# or memr# occurs, the piix/piix3 negates xdir#. for dma read cycles from the x-bus, xdir# is asserted from dackx# falling and negated from dackx# rising. at all other times, xdir# is negated. xoe# o x-bus output enable: xoe# is tied directly to the output enable of a 74f245 that buffers the x-bus data (xd[7:0]) from the system data bus (sd[7:0]). xoe# is asserted when a piix/piix3 supported x-bus device is decoded, and the devices decode is enabled in the x-bus chip select enable register (xbcs register). xoe# is asserted from the falling edge of the isa commands (ior#, iow#, memr#, or memw#) for pci master and isa master-initiated cycles. xoe# is negated from the rising edge of the isa command signals for cpu and pci master-initiated cycles and the sa[16:0] and la[23:17] address for isa master-initiated cycles. xoe# is not generated during any access to an x-bus peripheral in which its decode space has been disabled. dd15/ pcs# o programmable chip select: pcs# is asserted for isa i/o cycles that are generated by pci masters and subtractively decoded to isa, if the access hits the address range programmed into the pcsc register. the x-bus buffer signals are enabled when the chip select is asserted (i.e., it is assumed that the peripheral that is selected via this pin resides on the x- bus). bioscs# o bios chip select: bioscs# is asserted during read or write accesses to bios. bioscs# is driven combinatorially from the isa addresses sa[16:0] and la [23:17], except during dma. during dma cycles, bioscs# is not generated. kbcs# o keyboard controller chip select: kbcs# is asserted during i/o read or write accesses to kbc locations 60h and 64h. this signal is driven combinatorially from the isa addresses sa[16:0] and la [23:17]. for dma cycles, kbcs# is never asserted. rtccs# o real time clock chip select: rtccs# is asserted during read or write accesses to rtc location 71h. rtccs# can be tied to a pair of external or gates to generate the real time clock read and write command signals. rtcale o real time clock address latch: rtcale is used to latch the appropriate memory address into the rtc. a write to port 70h with the appropriate rtc memory address that will be written to or read from, causes rtcale to be asserted. rtcale is asserted based on iow# falling and remains asserted for two sysclks.
82371fb (piix) and 82371sb (piix3) e 18 signal name type description ferr# i numeric coprocessor error: this signal is tied to the coprocessor error signal on the cpu. ignne# is only used if the piix/piix3 coprocessor error reporting function is enabled in the xbcsa register. if ferr# is asserted, the piix/piix3 generates an internal irq13 to its interrupt controller unit. the piix/piix3 then asserts the intr output to the cpu. ferr# is also used to gate the ignne# signal to ensure that ignne# is not asserted to the cpu unless ferr# is active. ferr# has a weak internal pull-up used to ensure a high level when the coprocessor error function is disabled. ignne# od ignore error: this signal is connected to the ignore error pin on the cpu. ignne# is only used if the piix/piix3 coprocessor error reporting function is enabled in the xbcsa register. if ferr# is asserted, indicating a coprocessor error, a write to the coprocessor error register (f0h) causes the ignne# to be asserted. ignne# remains asserted until ferr# is negated. if ferr# is not asserted when the coprocessor error register is written, the ignne# signal is not asserted. 1.10. apic bus signals (piix3 only) signal name type description dd14/ apiccs# i/o o apic chip select (piix3 only). this active low output signal is asserted when the apic chip select is enabled and a pci originated cycle is positively decoded within the programmed ioapic address space. the default addresses of the ioapic are memory fec0_0000h and fec0_0010h. system design note: the dd[14]/apiccs# signal is demuxed externally with a 245 transceiver. the output of the transceiver drives the ioapics cs# signal. at certain times the transceiver floats its outputs, therefore a pullup resistor on the output of the tranceiver is required to keep this signal negated. testin#/ apicreq# i apic request (piix3 only). this signal has two functions, depending on the programming of the apic chip select bit (xbcs register). see the test signal description for the testin# function. apicreq# is asserted by an external apic device prior to sending an interrupt over the apic serial bus. when the piix3 samples this pin active it flushes its f-type dma buffers pointing towards pci. once the buffers are flushed, the piix3 asserts apicack# to inform the external apic that it can proceed to send the apic interrupt. apicreq# must be synchronous to pciclk. pcirst#/ apicack# o o apic acknowledge (piix3 only) . this signal has two functions, depending on the programming of the apic chip select bit (xbcs register). see the system reset signal description for the pcirst# function. the piix3 asserts apicack# after its internal buffers are flushed in response to the apicreq# signal. when the ioapic samples this signal asserted it knows that the piix3s buffers are flushed and that it can proceed to send the apic interrupt. the signal is driven from the rising edge of pciclk and is negated while pcirst# is asserted.
e 82371fb (piix) and 82371sb (piix3) 19 1.11. universal serial bus signals (piix3 only) signal name type description usbclk i universal serial bus clock. this signal clocks the universial serial bus clock. usbp0+ usbp0- i/o universal serial bus port 0. these signals are the differential data pair for serial port 0. usbp1+ usbp1- i/o universial serial bus port 1. these signals are the differential data pair for serial port 1. 1.12. system reset signals signal name type description pwrok i power ok: when asserted, pwrok is an indication to the piix/piix3 that power and pciclk have been stable for at least 1 ms. pwrok can be driven asynchronously. when pwrok is negated, the piix/piix3 asserts cpurst, pcirst# and rstdrv. when pwrok is asserted, the piix/piix3 negates cpurst, pcirst#, and rstdrv. cpurst od cpu reset: the piix/piix3 asserts cpurst to reset the cpu. the piix/piix3 asserts cpurst during power-up and when a hard reset sequence is initiated through the rc register. cpurst is driven synchronously to the rising edge of pciclk. if a hard reset is initiated through the rc register, the piix/piix3 resets it's internal registers to the default state. pcirst#/ apicack# (piix3 only) o o pci reset: this signal has two functions, depending on the programming of the apic chip select bit (xbcs register). see the apic signal description for the apicack# function. the piix/piix3 asserts pcirst# to reset devices that reside on the pci bus. the piix/piix3 asserts pcirst# during power-up and when a hard reset sequence is initiated through the rc register. pcirst# is driven inactive a minimum of 1 ms after pwrok is driven active. pcirst# is driven active for a minimum of 1ms when initiated through the rc register. pcirst# is driven asynchronously relative to pciclk. init od initialization: the piix/piix3 asserts init if it detects a shut down special cycle on the pci bus or if a soft reset is initiated via the rc register. rstdrv o reset drive: the piix/piix3 asserts this signal during a hard reset and during power-up to reset isa bus devices. rstdrv is also asserted for a minimum of 1 ms if a hard reset has been programmed in the rc register.
82371fb (piix) and 82371sb (piix3) e 20 1.13. test signals signal name type description testin#/ apicreq# (piix3 only) i i test input: this signal has two functions, depending on the programming of the apic chip select bit (xbcs register). see the apic signal description for the apicreq# function. the testin# signal is used in conjunction with the irq signals to select the various test modes of the piix/piix3. this input contains an internal pull up resistor. after a hard reset, this pin functions as a testin# signal. an external weak pull-up resistor (4.7k to 20k ohms) is required to 5v. 1.14. power and ground signals signal name type description vcc power (5 volts): this pin is connected to the 5 volt power supply. vcc3 (piix3) power (3.3 volts): this pin is connected to the 3.3 volt power supply. note that, if the the universal serial bus function is not used, this pin can be connected to the 5 volt power supply. gnd ground: this pin is connected to the ground plane.
e 82371fb (piix) and 82371sb (piix3) 21 1.15. signal state during reset table 1 shows the state of all piix/piix3 output and bi-directional signals during a hard reset. a hard reset is initiated when pwrok is asserted or by programming a hard reset through the rc register. table 1. output and i/o signal states during hard reset signal state ad[31:0] low (piix) tri-state (piix3) c/be[3:0]# low (piix) tri-state (piix3) frame# tri-state trdy# tri-state irdy# tri-state stop# tri-state devsel# tri-state par input phold# high (piix) tri-state (piix3) mdak[1:0]# (piix) high dd[15,13:0]/ pcs#,sbhe#, sa[19:8], dd14 (piix) tri-state dd14 (piix) dd14/apiccs# (piix3) tri-state high sa[7:0] undefined dior# high diow# high ddak[1:0]# high soe# high sdir high signal state la23/cs1s undefined la22/cs3s undefined la21/cs1p undefined la20/cs3p undefined la[19:17]/ da[2:0] undefined bale low aen depends on strapping option sysclk strapping option iochrdy tri-state ior# high iow# high memcs16# open drain memr# tri-state memw# tri-state smemr# high smemw# high sd[15:0] tri-state dack[7:5,3:0]# depends on strapping option tc strapping option refresh# tri-state spkr low intr open drain signal state pirqd# (piix3) tri-state nmi open drain smi# open drain stpclk# open drain xdir# high xoe# high bioscs# undefined (piix) high (piix3) kbcs# undefined (piix) high (piix3) rtccs# undefined (piix) high (piix3) rtcale low ferr# open drain ignne# open drain cpurst open drain usbp0+ usbp0- tri-state usbp1+ usbp1- tri-state pcirst# (piix) pcirst#/ apicack# (piix3) low init low rstdrv high
82371fb (piix) and 82371sb (piix3) e 22 2.0. register description the 82371fb piix internal registers are organized into five groups pci configuration registers (function 0), pci configuration registers (function 1), isa-compatible registers, pci bus master ide registers, and system power management registers. these registers are discussed in this section. the piix3 internal registers contain the same register sets as the piix plus two additional register sets for the universal serial bus (usb) functionpci configuration registers (function 2) and the usb i/o registers. some of the piix/piix3 registers contain reserved bits. software must deal correctly with fields that are reserved. on reads, software must use appropriate ma sks to extract the defi ned bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. in addition to reserved bits within a register, the piix/piix3 contains address locations in the pci configuration space that are marked "reserved". the piix/piix3 responds to accesses to these address locations by completing the host cycle. software s hould not write to reserved piix/piix3 configuration locations in the device-specific region (above address offset 3fh). during a hard reset, the piix/piix3 sets its internal registers to predetermined default states. the default values are indicated in the individual register descriptions. the following notation is used to describe register access attributes: ro read only . if a register is read only, writes have no effect. wo write only . if a register is write only, reads have no effect. r/w read/write . a register with this attribute can be read and written. note that individual bits in some read/write registers may be read only. r/wc read/write clear . a register bit with this attribute can be read and written. however, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. 2.1. register access table 2, table 3, and table 4 show the i/o assignments for the pci configuration registers (function 0, 1, and 2). table 5 shows the i/o assignments for the isa compatible registers. table 6 shows the i/o assignments for the bus master ide interface registers. table 7 shows the i/o assignments for the usb i/o registers. pci masters have access to all piix/piix3 internal registers. in addition, isa masters have access to some of the isa-compatible registers (see table 5). pci configuration registers (functions 0, 1, and 2) the 82371fb piix is a multi-function device on the pci bus implementing two functionspci-to-isa bridge (function 0) and ide interface (function 1). these functions can be independently configured with two sets of pci configuration registers in compliance with the pci local bus specification, revision 2.0. the two sets of configuration registers are accessed by the cpu through a mechanism defined for multi-functional pci devices. the piix does not assert devsel# for pci configuration cycles that target functions 2 through 7. the piix3 implements an additional pci bus function ? universial serial bus interface. the piix3 does not assert devsel# for pci configuration cycles that target functions 3 through 7.
e 82371fb (piix) and 82371sb (piix3) 23 isa compatible registers the isa-compatible registers (e.g., dma registers, timer/counter registers, x-bus registers, and nmi registers) are accessed through normal i/o space. except for the dma registers, the piix/piix3 positively decodes accesses to the isa-compatible registers. the piix/piix3 subtractively decodes accesses to all i/o space registers contained within the isa-compatible dma function. this permits another device in the system to implement the compatible dma function. pci master accesses to the isa-compatible registers can be 8, 16, 24, or 32 bits. however, the piix/piix3 only responds to the least significant byte. on writes the other bytes are not loaded and on reads the other bytes have invalid data. the piix/piix3 responds as an 8-bit isa i/o slave when accessed by an isa master. see the pci local bus ide section for accesses to the ide register blocks located in the ide device in general, accesses from cpu or pci masters to the internal piix/piix3 registers are not broadcast to the isa bus. exceptions to this are read/write accesses to 70h and f0h and write accesses to 80h, 84 C86h, 88h, 8cC8eh, 90h, 94C96h, 98h, and 9cC9eh. these accesses are broadcast to the isa bus. note that aliasing of the 90C9fh to 80C8fh can be enabled/disabled via the isa controller recovery timer register. power management registers there are two power management registers located in normal i/o space. these registers are accessed (by pci bus masters) with 8-bit accesses. the other power management registers are located in pci configuration space for function 0. pci bus master ide registers the pci bus master ide function uses 16 bytes located in normal i/o space, allocated via the bmiba register (a pci base address register). all bus master ide i/o space registers can be accessed as 8, 16, or 32-bit quantities. universal serial bus registers a set of usb registers provide control and status information for the host controller and two usb ports (table 7). this block of registers is i/o mapped into pci i/o space and control variouos operations of the usb host controller. the registers are relocateable via the usbbase register which is located in function 0 pci configuration space. table 2. pci configuration registers function 0 (pci to isa bridge) configuration offset mnemonic register register access 00 C01h vid vendor identification ro 02C03h did device identification ro 04C05h pcicmd pci command r/w 06C07h pcists pci device status r/wc 08h rid revision identification ro 09 - 0bh classc class code ro 0cC0dh reserved 0eh hedt header type ro
82371fb (piix) and 82371sb (piix3) e 24 configuration offset mnemonic register register access 0f C4bh reserved 4ch iort isa i/o controller recovery timer r/w 4dh reserved 4eh (piix) 4eC4fh (piix3) xbcs x-bus chip select enable r/w 4fC5fh (piix) 50C5fh (piix3) reserved 60C63h pirqrc[a:d] pci irq route control r/w 64C68h reserved 69h tom top of memory r/w 6aC6bh mstat miscellaneous status r/w 6cC6fh reserved 70h mbirq0 motherboard irq route control 0 r/w 71h mbirq1 motherboard irq route control 1 (piix) r/w reserved (piix3) 72C75h reserved 76C77h mbdma[1:0] motherboard dma control r/w 78C79h pcsc programmable chip select control r/w 7aC7fh reserved 80h reserved (piix) apicbase apic base address relocation (piix3) r/w 81h reserved 82h reserved (piix) dlc deterministic latency control (piix3) r/w 83C9fh reserved a0h smicntl smi control r/w a1h reserved a2Ca3h smien smi enable r/w a4Ca7h see system event enable r/w a8h ftmr fast off timer r/w a9h reserved aaCabh smireq smi request r/w
e 82371fb (piix) and 82371sb (piix3) 25 configuration offset mnemonic register register access ach ctltmr clock scale stpclk# low timer r/w adh reserved aeh cthtmr clock scale stpclk# high timer r/w afCffh reserved table 3. pci configuration registers function 1 (ide interface) configuration offset mnemonic register register access 00 C01h vid vendor identification ro 02C03h did device identification ro 04C05h pcicmd command r/w 06C07h pcists pci device status r/wc 08h rid revision identification ro 09 - 0bh classc class code ro 0ch reserved 0dh mlt master latency timer r/w 0eh hedt header type ro 0fC1fh reserved 20C23h bmiba bus master interface base address r/w 24C3fh reserved 40C43h idetim ide timing modes r/w 44h reserved (piix) sidetim slave ide timing modes (piix3) r/w 45Cffh reserved
82371fb (piix) and 82371sb (piix3) e 26 table 4. pci configuration registers function 2 (universial serial bus interface) (piix3 only) configuration offset mnemonic register register access 00 C01h vid vendor identification ro 02C03h did device identification ro 04C05h pcicmd command r/w 06C07h pcists device status r/wc 08h rid revision identification ro 09 - 0bh classc class code ro 0ch reserved 0dh lattmr latency timer r/w 0eh hedt header type ro 0fC19h reserved 20C23h baseadd io space base address r/w 24C3bh reserved 3ch il interrupt line r/w 3dh intrp interrupt pin ro 3eC5fh reserved. 60h sbrnum serial bus release number ro 61C69h reserved 6aC6bh mstat miscellaneous status r/w 6cCbfh reserved c0Cc1h legsup legacy support r/wc c2Cffh reserved
e 82371fb (piix) and 82371sb (piix3) 27 table 5. isa-compatible and power management registers address address (bits) type name access (hex) fedc ba98 7654 3210 0000h 3 0000 0000 000x 0000 r/w dma1 ch0 base and current address pci 0001h 3 0000 0000 000x 0001 r/w dma1 ch0 base and current count pci 0002h 3 0000 0000 000x 0010 r/w dma1 ch1 base and current address pci 0003h 3 0000 0000 000x 0011 r/w dma1 ch1 base and current count pci 0004h 3 0000 0000 000x 0100 r/w dma1 ch2 base and current address pci 0005h 3 0000 0000 000x 0101 r/w dma1 ch2 base and current count pci 0006h 3 0000 0000 000x 0110 r/w dma1 ch3 base and current address pci 0007h 3 0000 0000 000x 0111 r/w dma1 ch3 base and current count pci 0008h 3 0000 0000 000x 1000 r/w dma1 status(r) command(w) register pci 0009h 3 0000 0000 000x 1001 wo dma1 write request pci 000ah 3 0000 0000 000x 1010 wo dma1 write single mask bit pci 000bh 3 0000 0000 000x 1011 wo dma1 write mode pci 000ch 3 0000 0000 000x 1100 wo dma1 clear byte pointer pci 000dh 3 0000 0000 000x 1101 wo dma1 master clear pci 000eh 3 0000 0000 000x 1110 wo dma1 clear mask pci 000fh 3 0000 0000 000x 1111 r/w dma1 read/write all mask register bits pci 0020h 0000 0000 001x xx00 r/w int 1 control pci/isa 0021h 0000 0000 001x xx01 r/w int 1 mask pci/isa 0040h 0000 0000 010x 0000 r/w timer counter 1 - counter 0 count pci/isa 0041h 0000 0000 010x 0001 r/w timer counter 1 - counter 1 count pci/isa 0042h 0000 0000 010x 0010 r/w timer counter 1 - counter 2 count pci/isa 0043h 0000 0000 010x 0011 wo timer counter 1 command mode pci/isa 0060h 1 0000 0000 0110 0000 r reset xbus irq12/m and irq1 pci/isa 0061h 0000 0000 0110 0001 r/w nmi status and control pci/isa
82371fb (piix) and 82371sb (piix3) e 28 address address (bits) type name access (hex) fedc ba98 7654 3210 0070h 1 0000 0000 0111 0xx0 wo cmos ram address and nmi mask reg pci/isa 0080h 2,3 0000 0000 100x 0000 r/w dma page (reserved) pci/isa 0081h 3 0000 0000 100x 0001 r/w dma channel 2 page pci/isa 0082h 3 0000 0000 1000 0010 r/w dma channel 3 page pci/isa 0083h 3 0000 0000 100x 0011 r/w dma channel 1 page pci/isa 0084h 2,3 0000 0000 100x 0100 r/w dma page (reserved) pci/isa 0085h 2,3 0000 0000 100x 0101 r/w dma page (reserved) pci/isa 0086h 2,3 0000 0000 100x 0110 r/w dma page (reserved) pci/isa 0087h 3 0000 0000 100x 0111 r/w dma channel 0 page pci/isa 0088h 2,3 0000 0000 100x 0100 r/w dma page (reserved) pci/isa 0089h 3 0000 0000 100x 1001 r/w dma channel 6 page pci/isa 008ah 3 0000 0000 100x 1010 r/w dma channel 7 page pci/isa 008bh 3 0000 0000 100x 1011 r/w dma channel 5 page pci/isa 008ch 2,3 0000 0000 100x 1100 r/w dma page (reserved) pci/isa 008dh 2,3 0000 0000 100x 1101 r/w dma page (reserved) pci/isa 008eh 2,3 0000 0000 100x 1110 r/w dma page (reserved) pci/isa 008fh 3 0000 0000 100x 1111 r/w dma low page register refresh pci/isa 00a0h 0000 0000 101x xx00 r/w int 2 control pci/isa 00a1h 0000 0000 101x xx01 r/w int 2 mask pci/isa 00b2h 0000 0000 1011 0010 r/w advanced power management control pci 00b3h 0000 0000 1011 0011 r/w advanced power management status pci 00c0h 3 0000 0000 1100 000x r/w dma2 ch0 base and current address pci 00c2h 3 0000 0000 1100 001x r/w dma2 ch0 base and current count pci 00c4h 3 0000 0000 1100 010x r/w dma2 ch1 base and current address pci 00c6h 3 0000 0000 1100 011x r/w dma2 ch1 base and current count pci 00c8h 3 0000 0000 1100 100x r/w dma2 ch2 base and current address pci
e 82371fb (piix) and 82371sb (piix3) 29 address address (bits) type name access (hex) fedc ba98 7654 3210 00cah 3 0000 0000 1100 101x r/w dma2 ch2 base and current count pci 00cch 3 0000 0000 1100 110x r/w dma2 ch3 base and current address pci 00ceh 3 0000 0000 1100 111x r/w dma2 ch3 base and current count pci 00d0h 3 0000 0000 1101 000x r/w dma2 status(r) command(w) pci 00d2h 3 0000 0000 1101 001x wo dma2 write request pci 00d4h 3 0000 0000 1101 010x wo dma2 write single mask bit pci 00d6h 3 0000 0000 1101 011x wo dma2 write mode pci 00d8h 3 0000 0000 1101 100x wo dma2 clear byte pointer pci 00dah 3 0000 0000 1101 101x wo dma2 master clear pci 00dch 3 0000 0000 1101 110x wo dma2 clear mask pci 00deh 3 0000 0000 1101 111x r/w dma2 read/write all mask register bits pci 00f0h 1 0000 0000 1111 0000 wo coprocessor error pci/isa 04d0h 0000 0100 1101 0000 r/w int-1 edge/level control pci/isa 04d1h 0000 0100 1101 0001 r/w int-2 edge/level control pci/isa 0cf9h 0000 1100 1111 1001 r/w reset control pci notes: 1. read and write accesses to these locations are always broadcast to the isa bus. 2. write accesses to these locations are broadcast to the isa bus. read accesses are not. piix: if programmed in the isa controller recovery timer register, the piix will not alias the 90h-9fh address range with the following addresses: 80h, 84 - 86h, 88h, and 8c - 8eh. in this case accesses to the 90h - 9fh address range for the previously specified addresses are forwarded to the isa bus for both reads and writes and are ignored during isa master cycles (i.e., they are no-longer considered piix registers). note, that port 92 is always a distinct isa register and is always forwarded to the isa bus. piix3: if programmed in the isa controller recovery timer register, the piix3 does not alias the entire 90h-9fh address range. these locations are considered isa bus register locations and not piix3 registers. 3. isa-compatible dma register i/o space accesses are always subtractively decoded.
82371fb (piix) and 82371sb (piix3) e 30 table 6. pci bus master ide i/o registers offset from base address mnemonic register register access 00h bmicp bus master ide command (primary) r/w 01h reserved 02h bmisp bus master ide status (primary) r/wc 03h reserved 04C07h bmidtpp bus master ide descriptor table pointer (primary) r/w 08h bmics bus master ide command (secondary) r/w 09h reserved 0ah bmiss bus master ide status (secondary) r/wc 0bh reserved 0cC0fh bmidtps bus master ide descriptor table pointer (secondary) r/w note: the base address is programmable via the bmiba register (20 - 23h; function 1) table 7. usb host/controller i/o registers i/o address mnemonic register description register access base + (00 - 01h) usbcmd usb command r/w base + (02 - 03h) usbsts usb status r/wc base + (04 - 05h) usbintr usb interrupt enable r/w base + (06 - 07h) frnum frame number r/w** base + (08 - 0bh) frbaseadd frame list base address r/w base + 0ch sofmod start of frame modify r/w base + (10 - 11h) portsc1 port 1 status/control r/wc** base + (12 - 13h) portsc2 port 2 status/control r/wc** ** note: these registers are word writeable only. byte writes to these registers have unpredictable effects.
e 82371fb (piix) and 82371sb (piix3) 31 2.2. pci configuration registers pci to isa bridge (function 0) 2.2.1. vid vendor identification register (function 0) address offset: 00 C01h default value: 8086h attribute: read only the vid register contains the vendor identification number. this register, along with the device identification register, uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification number. this is a 16-bit value assigned to intel. 2.2.2. did device identification register (function 0) address offset: 02 C03h default value: 122eh (piix) 7000h (piix3) attribute: read only the did register contains the device identification number. this register, along with the vid register, define the piix. writes to this register have no effect. bit description 15:0 device identification number. this is a 16-bit value assigned to the piix. 2.2.3. pcicmd command register (function 0) address offset: 04 C05h default value: 0007h attribute: read/write this 16-bit register provides basic control over the piix's ability to respond to pci cycles. bit description 15:10 reserved. read as 0. 9 fast back-to-back enable. (not implemented) this bit is hardwired to 0. 8 piix: reserved. read as 0. piix3: serr# enable (serre). 1=enable. 0=disable. when enabled (and bit 3=1 in the dlc register), a delayed transaction timeout causes the piix3 to assert the serr# signal. the pcists register reports the status of the serr# signal. 7:5 reserved. read as 0. 4 postable memory write enable. (not implemented) this bit is hardwired to 0. 3 special cycle enable (sce) . 1=enable, the piix/piix3 recognizes shutdown special cycle. 0=disable, the piix/piix3 ignores all pci special cycles.
82371fb (piix) and 82371sb (piix3) e 32 bit description 2 bus master enable (bme). (not implemented) the piix/piix3 does not support disabling its bus master capability. this bit is hardwired to 1. 1 memory access enable (mae). (not implemented) the piix/piix3 does not support disabling access to main memory. this bit is hardwired to 1. 0 i/o space access enable (iose). the piix/piix3 does not support disabling its response to pci i/o cycles. this bit is hardwired to 1. 2.2.4. pcists pci device status register (function 0) address offset: 06 C07h default value: 0200h attribute: read/write clear the pcists register reports the occurrence of a pci master-abort by the piix/piix3 or a pci target-abort when the piix/piix3 is a master. the register also indicates the piix/piix3 devsel# signal timing. bit description 15 detected parity error (perr). (not implemented) read as 0. 14 piix: signaled serr# status (serrs). (not implemented) read as 0. piix3: signaled serr# status (serrs) r/wc. when the piix3 asserts the serr# signal, this bit is set to 1. software sets this bit to a 0 by writing a 1 to it 13 master-abort status (ma)r/wc. when the piix, as a master (for the isa bridge function), generates a master-abort, ma is set to a 1. software sets ma to 0 by writing a 1 to this bit location. 12 received target-abort status (rta)r/wc. when the piix/piix3 is a master on the pci bus (for the isa bridge function) and receives a target-abort, this bit is set to a 1. software sets rta to 0 by writing a 1 to this bit location. 11 signaled target-abort status (sta)r/wc. this bit is set when the piix/piix3 isa bridge function is targeted with a transaction that the piix/piix3 terminates with a target abort. software sets sta to 0 by writing a 1 to this bit location. 10:9 devsel# timing status (devt)ro. the piix/piix3 always generates devsel# with medium timing for isa functions. thus, devt=01. this devsel# timing does not include configuration cycles. 8 perr# response. (not implemented) read as 0. 7 fast back to backro. this bit indicates to the pci master that piix/piix3 as a target is capable of accepting fast back-to-back transactions. 6:0 reserved. read as 0s.
e 82371fb (piix) and 82371sb (piix3) 33 2.2.5. rid revision identification register (function 0) address offset: 08h default value: refer to applicable specification update document attribute: read only this 8 bit register contains device stepping information. writes to this register have no effect. bit description 7:0 revision id byte. the register is hardwired to the default value. 2.2.6. classc ? class code register (function 0) address offset: 09 - 0bh default value: 060100h attribute: read only this register contains the device programming interface information related to the sub-class code and base class code definition for the piix3 (function 0). this register also identifies the base class code and the function sub-class in relation to the base class code. bit description 23:1 6 base class code (basec). 06h=bridge device. 15:8 sub-class code (scc) . 01h=pci-to-isa bridge. 7:0 programming interface (pi). 00h=hardwired as a pci-to-isa bridge. 2.2.7. hedtheader type register (function 0) address offset: 0eh default value: 80h attribute: read only the hedt register identifies the piix/piix3 as a multi-function device. bit description 7:0 device type (devicet). 80h=multi-function device. 2.2.8. iortisa i/o recovery timer register (function 0) address offset: 4ch default value: 4dh attribute: read/write the i/o recovery mechanism in the piix/piix3 is used to add additional recovery delay between cpu or pci master originated 8-bit and 16-bit i/o cycles to the isa bus. the piix/piix3 automatically forces a minimum delay of 3.5 sysclks between back-to-back 8 and 16-bit i/o cycles to the isa bus. this delay is measured from the rising edge of the i/o command (ior# or iow#) to the falling edge of the next i/o command. if a delay of greater than 3.5 sysclks is required, the isa i/o recovery time register can be programmed to
82371fb (piix) and 82371sb (piix3) e 34 increase the delay in increments of sysclks. no additional delay is inserted for back-to-back i/o "sub cycles" generated as a result of byte assembly or disassembly. this register defaults to 8 and 16-bit recovery enabled with one sysclk clock added to the standard i/o recovery. bit description 7 dma reserved page register aliasing control (dmaac). when dmaac=0, the piix/piix3 aliases i/o accesses in the 90 C9fh range to the 80C8fh range. in this case, the piix/piix3 only forwards write accesses to these locations to the isa bus. piix: when dmaac=1, the piix disables aliasing for the following registers; 80h, 84 - 86h, 88h, and 8c - 8eh. when disabled, the piix forwards read and write accesses to these registers to the isa. piix3: when dmaac=1, the piix3 disables aliasing for the entire 90C9fh range (they are considered isa bus register locations). when disabled, the piix3 forwards read ands write accesses to these registers to isa. note, that port 92h is always a distinct isa register in the 90C9fh range and is always forwarded to the isa bus. when dmaac=1, isa master accesses to the 90C9fh range are ignored by the piix. also, when dmaac=1, the piix/piix3 does not re-load the power management fast-off-timer with its original value for accesses to the 90C9fh address range. 6 8-bit i/o recovery enable. 1=enable the recovery time programmed in bits [5:3]. 0=disable recovery times in bits [5:3] and the recovery timing of 3.5 sysclks is inserted. 5:3 8-bit i/o recovery times. when bit 6=1, this 3-bit field defines the recovery time for 8-bit i/o. bit[5:3] sysclk bit[5:3] sysclk 001 1 101 5 010 2 110 6 011 3 111 7 100 4 000 8 2 16-bit i/o recovery enable. 1=enable, the recovery times programmed in bits [1:0]. 0=disable, programmable recovery times in bits [1:0] and the recovery timing of 3.5 sysclks is inserted. 1:0 16-bit i/o recovery times. when bit 2=1, this 2-bit defines the recovery time for 16-bit i/o. bit[1:0] sysclk 01 1 10 2 11 3 00 4 2.2.9. xbcs x-bus chip select register (function 0) address offset: 4eh (piix) 4e - 4fh (piix3) default value: 03h attribute: read/write this register enables/disables accesses to the rtc, keyboard controller, ioapic (piix3 only), and bios. disabling any of these bits prevents the chip select and x-bus output enable control signal (xoe#) for that device from being generated. this register also provides coprocessor error and mouse functions.
e 82371fb (piix) and 82371sb (piix3) 35 bit description 15:9 piix3: reserved. 8 piix3: apic chip select. when enabled (bit 8=1), apiccs# is asserted for pci memory accesses to the programmable ioapic region. this cycle is forwarded to the isa bus. the default ioapic addresses are memory fec0_0000h and fec0_0010h. these can be relocated via the apic base address relocation register. when disabled (bit 8=0), the pci cycle is ignored by piix3 and apiccs# and xoe# are not generated. note that apiccs# is not generated for isa-originated cycles. this bit also controls the function of two shared signals on the piix3 as shown below: shared signal name bit 8=0 bit 8=1 testin#/apicreq# testin# apicreq# pcirst#/apicack# pcirst# apicack# 7 extended bios enable. when bit 7=1 (enabled), pci master accesses to locations fff80000 Cfffdffffh are forwarded to isa and result in the generation of bioscs# and xoe#. when forwarding the additional 384-kbyte region at the top of 4 gbytes, the piix/piix3 allows the pci address a[23:20] to propagate to the isa la[23:20] lines as all 1's, aliasing this 384-kbyte region to the top of the 16-mbyte space. to avoid contention, isa addin memory must not be present in this region (00f80000C00fdffffh). when bit 7=0, the piix/piix3 does not generate bioscs# or xoe#. 6 lower bios enable. when bit 6=1 (enabled), pci master, or isa master accesses to the lower 64-kbyte bios block (e0000Ceffffh) at the top of 1 mbyte, or the aliases at the top of 4 gbyte (fffe0000Cfffeffffh) result in the generation of bioscs# and xoe#. when forwarding the region at the top of 4 gbytes to the isa bus, the isa la[23:20] lines are all 1's, aliasing this region to the top of the 16-mbyte space. to avoid contention, isa addin memory must not be present in this region (00f80000C00fdffffh). when bit 6=0, the piix/piix3 does not generate bioscs# or xoe# during these accesses and does not forward the accesses to isa. 5 coprocessor error function enable. 1=enable; the ferr# input, when asserted, triggers irq13 (internal). ferr# is also used to gate the ignne# output. 4 irq12/m mouse function enable. 1=mouse function; 0=standard irq12 interrupt function. 3 reserved. 2 bioscs# write protect enable. 1=enable (bioscs# is asserted for bios memory read and write cycles in decoded bios region); 0=disable (bioscs# is only asserted for bios read cycles). 1 keyboard controller address location enable. 1=enable kbcs# and xoe# for address locations 60h and 64h. 0=disable kbcs#/xoe# for accesses to these locations. 0 rtc address location enable. 1=enable rtccs#/rtcale and xoe# for accesses to address locations 70C77h. 0=disable rtccs#/rtcale and xoe# for these accesses.
82371fb (piix) and 82371sb (piix3) e 36 2.2.10. pirqrc[a:d] pirqx route control registers (function 0) address offset : 60h (pirqrca#) 63h (pirqrcd#) default value: 80h attribute: r/w these registers control the routing of the pirq[a:d]# signals to the irq inputs of the interrupt controller. each pirqx# can be independently routed to any one of 11 interrupts. all four pirqx# lines can be routed to the same irqx input. note that the irq that is selected through bits [3:0] must be set to level sensitive mode in the corresponding elcr register. when a pirq signal is routed to an interrupt controller irq, the piix/piix3 masks the corresponding irq signal. bit description 7 interrupt routing enable. 0=enable; 1=disable 6:4 reserved. read as 0s. 3:0 interrupt routing. when bit 7=0, this field selects the routing of the pirqx to one of the interrupt controller interrupt inputs. bits[3:0] irq routing bits[3:0] irq routing bits[3:0] irq routing 0000 reserved 0110 irq6 1011 irq11 0001 reserved 0111 irq7 1100 irq12 0010 reserved 1000 reserved 1101 reserved 0011 irq3 1001 irq9 1110 irq14 0100 irq4 1010 irq10 1111 irq15 0101 irq5 2.2.11. tom top of memory register (function 0) address offset: 69h default value: 02h attribute: read/write this register enables the forwarding of isa or dma memory cycles to the pci bus and sets the top of main memory accessible by isa or dma devices. in addition, this register controls the forwarding of isa or dma accesses to the lower bios region (e0000 Ceffffh) and the 512C640-kbyte main memory region (80000C 9ffffh). the top of memory configuration register must be set by the bios. bit description 7:4 top of memory. the top of memory can be assigned in 1-mbyte increments from 1C16 mbytes. isa or dma accesses within this region, and not in the memory hole region, are forwarded to pci. bits[7:4] top of memory bits[7:4] top of memory bits[7:4] top of memory 0000 1 mbyte 0110 7 mbyte 1011 12 mbyte 0001 2 mbyte 0111 8 mbyte 1100 13 mbyte 0010 3 mbyte 1000 9 mbyte 1101 14 mbyte 0011 4 mbyte 1001 10 mbyte 1110 15 mbyte 0100 5 mbyte 1010 11 mbyte 1111 16 mbyte 0101 6 mbyte note that the piix/piix3 only supports a main memory hole at the top of 16 mbytes. thus, if a 1-mbyte memory hole is created for the host-to-pci bridge dram controller between 15 and 16 mbytes, the piix/piix3 top of memory should be set at 15 mbytes.
e 82371fb (piix) and 82371sb (piix3) 37 bit description 3 isa/dma lower bios forwarding enable. 1=enable (forwarded to pci, if xbcs register bit 6=0); 0=disable (contained to isa). note that if the xbcs register bit 6=1, isa/dma accesses in this region are always contained to isa. 2 piix: reserved piix3: a,b segment forwarding enable. 1=enable (forward to pci), 0 = disable (default, contain to isa). when enabled, this bit allows isa master and dma memory accesses to a0000h - bffffh range to be forwarded to pci. when disabled, these accesses are contained to isa. 1 isa/dma 512 C640-kbyte region forwarding enable . 1=enable (forwarded to pci); 0=disable (contained to isa). 0 reserved 2.2.12. mstatmiscellaneous status register (function 0) address offset: 6b C6ah default value: undefined attribute: piix: read/write (bits [1:0] are read only) piix3: read/write clear(bits 1 is read only) this register provides miscellaneous status and control functions. bit description 15 piix: reserved. piix3: serr# generation due to delayed transaction ? r/wc. piix3 sets this bit to a 1 when it generates serr# due to a delayed transaction. software sets this bit to a 0 by writing a 1 to it. 14:8 reserved. 7 piix: reserved piix3: nb retry enable (nbre)--r/w, 1=enable, 0 = disable (default). this bit, when enabled, causes the piix3 to retry, without initiating a delayed transaction, cpu initiated, non-lock#, pci cycles. no delayed transactions to piix3 may currently be pending and passive release must be active. delayed transactions and passive release must both be enabled via the dlc register (function 0, offset 82h). when disabled, the piix3 accepts these cycles as normal, which may include retry with initiation of a delayed transaction.
82371fb (piix) and 82371sb (piix3) e 38 bit description 6 piix: reserved. piix3: extsmi# mode enable (esmime) ? r/w. 1=enable. 0=disable (default). this bit is used to enable a special serr# handling protocol between the host-to-pci bridge and the piix3. when esmime is enabled, the operating mode of the extsmi# signal is determined by the duration of the extsmi# signal. if the extsmi# signal is asserted for one pclk, an serr# is reported in the nmisc register (address 61h) and an nmi is generated, if enabled in the nmi registers (address 61h and 70h). if extsmi# is asserted for more than one pclk, the standard mode for handling extsmi# is used (i.e., same as when this bit is set to 0). when disabled (standard mode) and a falling edge is detected on extsmi#, an smi is signaled, if extsmi# signaling is enabled. host-to-pci bridge serr# gate not necessary if system extsmi# is not used system extsmi# (assumes minimum assertion of more than one pclk) extsmi# piix3 smi_nmi.drw 5 reserved. 4 piix: reserved. piix3: usb enable (usbe) ? r/w. 1=enable. 0=disable (default). when disabled, all usb functionality is disabled. this bit must be set to 1 to access function 2 configuration space. note that dynamically disabling usb is not supported in piix3. this bit is used to enable/disable the usb at boot time. in case software has to disable the usb during run time it has to do the following: software must turn off the master enable and i/o decode enable for function 2 (via the pcicmd register, function 2) prior to writing this bit to 0. 3 reserved. 2 piix: pci header type bit enable ? r/w. this bit controls the header type bit in the piix register 0eh which defines the piix as a multifunction device. this bit defaults to 1 (multifunction device) and should be left in the default state. piix3: reserved. 1 piix: internal isa dma or external dma mode status (iedmas) ? ro. 0=normal dma operation. this bit reports the strapping option selected on the tc signal (pulled high at reset for a value of 0). piix3: reserved,
e 82371fb (piix) and 82371sb (piix3) 39 bit description 0 piix: isa clock divisor status ? ro. this bit reports the strapping option on the sysclk signal. 1=clock divisor of 3 (pciclk=25 mhz). 0=clock divisor of 4 (pciclk=33 mhz). note that, for pciclk=30 mhz, a clock divisor of 4 must be selected and produces a sysclk of 7.5 mhz. piix3: isa clock divisor ? r/w. this bit controls the frequency of the sysclk signal. 1=clock divisor of 3 (pciclk=25 mhz). 0=clock divisor of 4 (pciclk=33 mhz). note that, for pciclk=30 mhz, a clock divisor of 4 must be selected and produces a sysclk of 7.5 mhz. the default value of this bit is determined by the strapping option on the sysclk signal. 2.2.13. mbirq[1:0] motherboard device irq route control registers (function 0) address offset : 70h mbirq0 (piix and piix3) 71hmbirq1 (piix only) default value: 80h attribute: r/w these registers control the routing of motherboard device interrupts (mirq[1:0]) to the internal irq inputs of the interrupt controller. each mirqx# can be independently routed to any one of 11 interrupts. note that, when an mirq line and a pirq# line are steered to the same isa interrupt, the device connected to the mirq line must be set for active high, level interrupts. in this case, the isa interrupt will be masked. bit 6 of that motherboard device irq route control register must be programmed to a 0. bit description 7 interrupt routing enable. 0=enable routing; 1=disable routing. 6 mirqx/irqx sharing enable. 0=disable sharing; 1=enable sharing. when sharing is disabled and bit 7 of this register is 0, the interrupt specified by bits [3:0] is masked. interrupt sharing should only be enabled when the device connected to the mirq line and the device connected to the isa irq line both produce active high, level interrupts. 5 piix: reserved piix3: irq0 enable, 1=enable (irq0 output), 0 = disable (default, mirq0 input). when enabled the mirq0/irq0 pin functions as the irq0 output and the ide interrupt status flag in bus master ide status register is set by the irq15 input signal. when disabled the mirq0/irq0 pin functions as the mirq0 input and the ide interrupt status flag in the bus master ide status register is set by the mirq0 input signal. 4 reserved. read as zero. 3:0 interrupt routing. when bit 7=0, this field selects the routing of the mbirqx to one of the interrupt controller interrupt inputs. bits[3:0] irq routing bits[3:0] irq routing bits[3:0] irq routing 0000 reserved 0110 irq6 1011 irq11 0001 reserved 0111 irq7 1100 irq12 0010 reserved 1000 reserved 1101 reserved 0011 irq3 1001 irq9 1110 irq14 0100 irq4 1010 irq10 1111 irq15 0101 irq5
82371fb (piix) and 82371sb (piix3) e 40 2.2.14. mbdma[1:0] motherboard device dma control registers (function 0) address offset : 76h mbdma0#; 77hmbdma1# default value: 0ch attribute: r/w for both the piix and piix3, these registers enable/disable a type f dma transfer (3 sysclk) for a particular dma channel. for the piix, these registers also control the routing of motherboard device dma signals (mdrq[1:0] and mdak[1:0]) to the dreq and dack# signals on the 8237 dma controller unit. bit description 7 type f and dma buffer enable (fast). 1=enable for the channel selected by bits[2:0]. 0=disable for the channel selected by bits[2:0]. 6:4 reserved. 3 piix: disable motherboard channel (dmc). when this bit 3=0, the mdrq/mdak# pair associated with this channel is routed to the compatable isa channel determined by the chnl field (bits[2:0]). when bit 3=1, the isa dreq/dack# pair is used for that channel. when a mdrq/mdak# pair is programmed for a given 8237 dma channel and dmc=0 (bit 3), the corresponding dreq/dack# pins are masked for that channel. when dmc=1, the mdrq/mdak# signals are masked. if both motherboard dmas are used, the motherboard dmas should be programmed to different compatible dma channels. programming both motherboard dmas to the same compatible dma channel results in unpredictable device operation. piix3: reserved. 2:0 piix: type f and motherboard dma channel routing (chnl). when dmc=0, this field steers the corresponding mdrq/mdak# signals to a compatable isa channel for a motherboard peripheral (and if fast=1, also enables type f transfers and the 4-byte dma buffer). when dmc=1 and fast=1, this field enables type f transfers and the 4-byte dma buffer for an isa peripheral on a given channel. piix3: type f dma channel routing (chnl). when fast=1, this field enables type f transfers and the 4-byte dma buffer for an isa peripheral on the selected channel. bits[2:0] dma channel bits[2:0] dma channel 000 0 100 default (disabled) 001 1 101 5 010 2 110 6 011 3 111 7 2.2.15. pcsc programmable chip select control register (function 0) address offset: 78 C79h default value: 0002h attribute: read/write this register controls the assertion of the pcs# programmable chip select signal. the pcs# signal is asserted for subtractively decoded i/o cycles generated by pci masters that fall in the range specified by this register. the address is programmable to any 16-bit i/o space location and the range is programmable to be 4, 8 or 16 bytes. a split range is precluded. the upper sixteen address bits (ad[31:16]) must be zero for the
e 82371fb (piix) and 82371sb (piix3) 41 address to be decoded and the pcs# signal asserted. the pcs# signal is never asserted for isa bus masters access. bit description 15:2 pcs address (pcsaddr). this field defines a 16-bit i/o space address (4 byte range) that causes the pcs# signal to assert. address bits [3:2] may be masked (considered "don't care") by programming bits [1:0] of this register. 1:0 pcs address mask. when bit 1=1, pcsaddr3 is masked. when bit 0=1, pcsaddr2 is masked. bits[1:0] range 00 4 bytes (default) 01 8 bytes, contiguous 10 disabled 11 16 bytes, contiguous 2.2.16. apicbase apic base address relocation register (function 0) (piix3 only) address offset: 80h default value: 00h attribute: read/write this register provides the modifier for the apic base address. apic is mapped in the memory space at the locations fec0_xy00h and fec0_xy10h (x=0-fh, y=0,4,8,ch). the value of 'y' is defined by bits [1,0] and the value of 'x' is defined by bits [5:2]. thus, the relocation register provides 1-kbyte address granularity (i.e., potentially up to 64 ioapics can be uniformly addresses in the memory space). the default value of 00h provides mapping of the ioapic unit at the addresses fec0_0000h and fec0_0010h. bit description 7 reserved. 6 a12 mask. this bit determines selects whether apiccs# is generated for one or two ioapic address ranges. when bit 6=1, address bit 12 is ignored allowing the apiccs# signal to be generated for two consecutive ioapic address ranges. external logic is needed to select individual ioapics by combining sa12 and apiccs#. for example, when bit 6=1 (and x and y = 0), apiccs# is generated for addresses fec0_0000h, fec0_0010, as well as fec0_1000h, fec0_1010. when bit 6=0, apiccs# is generated for one ioapic address range. 5:2 x-base address. bits[5:2] are compared with pci address bits ad[15:12], respectively. 1:0 y-base address. bits[1:0] are compared with pci address bits ad[11:10], respectively.
82371fb (piix) and 82371sb (piix3) e 42 2.2.17. dlc deterministic latency control register (function 0) (piix3 only) address offset: 82h default value: 00h attribute: read/write this register enables/disables the delayed transaction and passive release functions, respectively. when enabled, these functions make the piix3 pci revision 2.1 compliant. note that neither delayed completion nor passive release have any effect on bus master ide and type f dma transfers. the 2.1 revision of the pci specification requires much tighter controls on target and master latency. targets must respond with trdy# or stop# within 16 clo cks of frame#, and masters must assert irdy# within 8 pci clocks for any data phase. pci cycles to or from isa typically take l onger than this. the piix3 provides a programmable delayed completion mechanism described in the pci specification to meet the required target latencies. isa bridges also support gat mode, which will now violate the spirit of the pci specification. the piix3 provides a programmable passive release mechanism to meet the required master latencies. when passive release is enabled in the piix3, isa masters may see long delays in accesses to any pci memory, including the main dram array. the isa gat mode is not supported with passive release enabled. isa masters must honor iochrdy. bit description 7:4 reserved. 3 serr# generation due to delayed transaction timeout enable. 1=enable. 0=disable. 2 usb passive release enable (usbpr). 1=enable 0=disable. 1 passive release enable. 1=enable the passive release mechanism encoded on the phold# signal (default). 0=phold# functions identically to the way it did in the piix (82371fb). 0 delayed transaction enable. 1=enable the delayed transaction mechanism when the piix3 is the target of a pci transaction (default). 0=piix3 resonds as a target of a pci transaction identically to the way the piix (82371fb) responded.
e 82371fb (piix) and 82371sb (piix3) 43 2.2.18. smicntl smi control register (function 0) address offset: a0h default value: 08h attribute: read/write the smicntl register provides fast off timer control, stpclk# enable/disable, and cpu clock scaling. this register also enables/disables the system management interrupt (smi). bit description 7:5 reserved 4:3 fast off timer freeze (ctmrfrz). this field enables/disables the fast off timer and when enabled, selects the timer count granularity as shown below: bits[4:3] count granularity count granularity count granularity (33 mhz pciclk) (30 mhz pciclk) (25 mhz pciclk) 00 1 minute 1.1 minute 1.32 minute 01 disabled (default) disabled (default) disabled (default) 10 1 pciclk 1 pciclk 1 pciclk 11 1 msec 1.1 msec 1.32 msec 2 stpclk# scaling enable (cstpclksc). 1=enable; 0=disable. when enabled (and bit 1=1), the high and low times for the stpclk# signal are controlled by the clock scaling stpclk# high timer and clock scaling stpclk# low timer registers. 1 stpclk# signal enable (cstpclke). 1=enable; 0=disable. when enabled, an apmc register read causes stpclk# to be asserted. when disabled, the stpclk# signal is disabled and is negated (high). software can set this bit to 0 by writing a 0 to it. 0 smi# gate (csmigate). 1=enable; 0=disable. when enabled, a system management interrupt condition asserts the smi# signal. when disabled, the smi# signal is masked and negated. this bit only affects the smi# signal and does not affect the detection/recording of smi events (i.e., this bit does not effect the smi status bits in the smireq register). thus, if an smi is pending when this bit is set to 1, the smi# signal is asserted. 2.2.19. smiensmi enable register (function 0) address offset: a2 - a3h default value: 0000h attribute: read/write this register enables the generation of smi (asserting the smi# signal) for the associated hardware events (bits [5:0]), and software events (bit 7). when a hardware event is enabled, the occurrence of a corresponding event results in the assertion of smi#, if enabled via the smicntl register. the smi# is asserted independent of the current power state (power-on or fast off). the default for all sources in this register is disabled. bit description 15:9 reserved. 8 piix: reserved. piix3: legacy usb smi enable 1=enable usb legacy logic to generate smi#. 0=disable (default).
82371fb (piix) and 82371sb (piix3) e 44 bit description 7 apmc write smi enable. 1=enable; 0=disable. 6 extsmi# smi enable. 1=enable; 0=disable. 5 fast off timer smi enable. 1=enable; 0=disable. when enabled, the timer generates an smi when it decrements to zero. 4 irq12 smi enable (ps/2 mouse interrupt). 1=enable; 0=disable. 3 irq8 smi enable (rtc alarm interrupt). 1=enable; 0=disable. 2 irq4 smi enable ( c om2/com4 interrupt or mouse). 1=enable; 0=disable. 1 irq3 smi enable (com1/com3 interrupt or mouse). 1=enable; 0=disable. 0 irq1 smi enable (keyboard interrupt). 1=enable; 0=disable. 2.2.20. see system event enable register (function 0) address offset: a4 Ca7h default value: 00000000h attribute: read/write this register enables hardware events as system events and break events for power management control. the default for each system/break event in this register is disabled. system events : activity by these events can keep the system from powering down. when a system event is enabled, the corresponding hardware event activity prevents a fast off powerdown condition by reloading the fast off timer with its initial count. break events : these events can awaken a powered down system. when a break event is enabled, the corresponding hardware event activity powers up the system by negating stpclk#. bit description 31 fast off smi enable (fsmien). 1=enable (system and break events); 0=disable. 30 intr enable (fintren). 1=enable (break event); 0=disable. when enabled, intr is used as a global break event. in this case, any irq that is generated causes the system to powerup via the negation of stpclk#, regardless of the state of bits[15:3,1:0] in this register. for the piix3, this function should be disabled if an external ioapic is used. 29 fast off nmi enable (fnmien). 1=enable (system and break events); 0=disable. 28 82371fb piix: reserved. piix3: fast off apic enable (fapicen). 1=enable (break event); 0=disable. 27:16 reserved 15:3 fast off irq[15:3] enable (firq[15:3]en). 1=enable (system and break events); 0=disable. 2 reserved. 1:0 fast off irq[1:0] enable (firq[1:0]en). 1=enable (system and break events); 0=disable.
e 82371fb (piix) and 82371sb (piix3) 45 2.2.21. ftmr fast off timer register (function 0) address offset: a8h default value: 0fh attribute: read/write the fast off timer indicates (through an smi) that the system has been idle for a pre-programmed period of time. when the timer expires, an smi special cycle is generated. the count time interval is programmable (via the smicntl register). the granularity of the counter is programmable via the smicntl register. note before writing to the ftmr register, the fast off timer must be stopped via bits [4:3] of the smicntl register. bit description 7:0 fast off timer value. bits [7:0] contain one less than the actual count-down value. thus, if x is programmed into this register, the countdown value is x+1. the x+1 value is loaded into the counter when an enabled system event occurs. when the fast off timer reaches 00h, an smi is generated and the timer is re-loaded with the x+1 value. when the fast off timer is enabled (via the smicntl register), the timer counts down from this value. a read from the ftmr register returns the value last written. 2.2.22. smireqsmi request register (function 0) address offset: aa Cabh default value: 00h attribute: read/write the smireq register contains status bits indicating which enabled event caused an smi. note 1. the smireq bits are set, cleared, or read independently of each other and independently of the csmigate bit in the smicntl register. 2. if software attempts to set a status bit to 0 at the same time that the piix/piix3 is setting it to 1, the bit is set to 1. 3. each of the smireq bits is set by the piix/piix3 in response to the activation of the corresponding smi event. if the smi event is still active when the corresponding smireq bit is set to 0, the piix/piix3 does not set the status bit back to a 1 (i.e., there is only one status indication per active smi event). 4. when an irqx signal is asserted, the corresponding irqx status bit is set to a 1. if the irqx signal is still active when software sets the corresponding status bit to 0, the status bit is not set back to a 1. the irqx may be negated before software sets the status bit to 0. however, if the status bit is set to 0 at the same time a new irqx is activated, the status bit remains at 1. this indicates to the smi handler that a new smi event has been detected. 5. if an irqx is set in level mode and shared by two devices, the irq should not be enabled as an smi# event. the piix's smireq bits are essentially set with an edge. when the second irq occurs on a shared irq, there is no second edge and the smi# will not be generated for the second irq.
82371fb (piix) and 82371sb (piix3) e 46 bit description 15:9 reserved 8 piix: reserved. piix3: legacy usb smi status (rlusb). this bit is set to 1 to indicate that the usb legacy keyboard logic caused an smi. software sets this bit to a 0 by writing a 0 to it. 7 apm smi status (rapmc). this bit is set to 1 to indicate that a write to the apm control register caused an smi. software sets this bit to a 0 by writing a 0 to it. 6 extsmi# smi status (rext). this bit is set to 1 to indicate that extsmi# caused an smi. software sets this bit to a 0 by writing a 0 to it. for the piix3, the extsmi# signal can be used to provide a special protocol between the host-to-pci bridge and the piix3 (see mstat register description, 82h, function 0). 5 fast off timer expired status (rfot). this bit is set to 1 to indicate that the fast off timer expired and caused an smi. software sets this bit to a 0 by writing a 0 to it. note that the timer re-starts counting one the next clock after it expires. 4 irq12 request smi status (rirq12). this bit is set to 1 to indicate that irq12 caused an smi. software sets this bit to a 0 by writing a 0 to it. 3 irq8# request smi status (rirq8). this bit is set to 1 to indicate that irq8# caused an smi. software sets this bit to a 0 by writing a 0 to it. 2 irq4 request smi status (rirq4). this bit is set to 1 to indicate that irq4 caused an smi. software sets this bit to a 0 by writing a 0 to it. 1 irq3 request smi status (rirq3). this bit is set to 1 to indicate that irq3 caused an smi. software sets this bit to a 0 by writing a 0 to it. 0 irq1 request smi status (rirq1). this bit is set to 1 to indicate that irq1 caused an smi. software sets this bit to a 0 by writing a 0 to it. 2.2.23. ctltmr clock scale stpclk# low timer (function 0) address offset: ach default value: 00h attribute: read/write the value in this register defines the duration of the stpclk# asserted period when bit 2 in the smicntl register is set to 1. the value in this register is loaded into the stpclk# timer when stpclk# is asserted. the stpclk# timer is a divide by pci clock. the base count for a value of 0 is 42 m sec for a 50 mhz time base, 35 m sec for a 60 mhz time base, 32 m sec for a 66 mhz time base. these numbers are determined as follows: # of pci clocks stpclk# is asserted (or negated) = 1 + 1056 x (programmed value in register +1). bit description 7:0 clock scaling stpclk# low timer value. bits [7:0] define the duration of the stpclk# asserted period during clock throttling.
e 82371fb (piix) and 82371sb (piix3) 47 2.2.24. cthtmr clock scale stpclk# high timer (function 0) address offset: aeh default value: 00h attribute: read/write the value in this register defines the duration of the stpclk# negated period when bit 2 in the smicntl register is set to 1. the value in this register is loaded into the stpclk# timer when stpclk# is negated. the stpclk# timer is a divide by pci clock. the base count for a value of 0 is 42 m sec for a 50 mhz time base, 35 m sec for a 60 mhz time base, 32 m sec for a 66 mhz time base. these numbers are determined as follows: # of pci clocks stpclk# is asserted (or negated) = 1 + 1056 x (programmed value in register +1). bit description 7:0 clock scaling stpclk# high timer value. bits [7:0] define the duration of the stpclk# negated period during clock throttling. 2.3. pci configuration registers ide interface (function 1) the piix/piix3 are multi-function devices, as indicated by bit 7 of the header type register. the pci ide interface function uses function 1. 2.3.1. vid vendor identification register (function 1) address offset: 00 C01h default value: 8086h attribute: read only the vid register contains the vendor identification number. this register, along with the device identification register, uniquely identify any pci device. writes to this register have no effect. bit description 15:0 vendor identification number. this is a 16-bit value assigned to intel 2.3.2. did device identification register (function 1) address offset: 02 C03h default value: 1230h (piix) 7010h (piix3) attribute: read only the did register contains the device identification number. this register, along with the vid register, define the piix. writes to this register have no effect. bit description 15:0 device identification number. this is a 16-bit value assigned to the piix.
82371fb (piix) and 82371sb (piix3) e 48 2.3.3. pcicmd command register (function 1) address offset: 04 C05h default value: 0000h attribute: read/write the pcicmd register controls access to the i/o space registers. bit description 15:10 reserved. read 0. 9 fast back to back enable (fbe). (not implemented) this bit is hardwired to 0. 8:5 reserved. read as 0. 4 memory write and invalidate enable (mwi). (not implemented) this bit is hardwired to 0. 3 special cycle enable (sce). (not implemented) this bit is hardwired to 0 2 bus master functionenable (bme). 1=enable. 0=disable. 1 memory space enable (mse). (not implemented) this bit is hardwired to 1. 0 i/o space enable (iose). this bit controls access to the i/o space registers. when iose=1, access to the legacy ide ports (both primary and secondary) and the pci bus master ide i/o registers is enabled. the base address register for the pci bus master ide i/o registers should be programmed before this bit is set to 1. 2.3.4. pcists pci device status register (function 1) address offset: 06 C07h default value: 0280h attribute: read/write pcists is a 16-bit status register for the ide interface function. the register also indicates the piix's devsel# signal timing. bit description 15 detected parity error (perr). (not implemented) read as 0. 14 serr# status (serrs). (not implemented) read as 0. 13 master-abort status (mas) r/w. when the bus master ide interface function, as a master, generates a master abort, ma is set to a 1. software sets ma to 0 by writing a 1 to this bit. 12 received target-abort status (rta)r/w. when the bus master ide interface function is a master on the pci bus and receives a target abort, this bit is set to a 1. software sets rta to 0 by writing a 1 to this bit. 11 signaled target abort status (sta)r/w. this bit is set when the piix/piix3 ide interface function is targeted with a transaction that the piix/piix3 terminates with a target abort. software resets sta to 0 by writing a 1 to this bit.. 10:9 devsel# timing status (devt)ro. for the piix, devt=01 indicating medium timing for devsel# assertion when performing a positive decode. devsel# timing does not include configuration cycles.
e 82371fb (piix) and 82371sb (piix3) 49 bit description 8 data parity detected (dpd). (not implemented) read as 0. 7 fast back to back capable (fbc) ro. hardwired to 1. this bit indicates to the pci master that piix, as a target, is capable of accepting fast back-to-back transactions. 6:0 reserved . read as 0's. 2.3.5. ridrevision identification register (function 1) address offset: 08h default value: refer to applicable specification update document attribute: read only this 8 bit register contains device stepping information. writes to this register have no effect. bit description 7:0 revision id byte. the register is hardwired to the default value during manufacturing. 2.3.6. classc ? class code register (function 1) address offset: 09 - 0bh default value: 010180h attribute: read only this register contains the device programming interface information related to the sub-class code and base class code definition for the piix3 (function 1). this register also identifies the base class code and the function sub-class in relation to the base class code. bit description 23:1 6 base class code (basec). 01h=mass storage device. 15:8 sub-class code (scc) . 01h=ide controller. 7:0 programming interface (pi). 80h=capable of ide bus master operation. 2.3.7. mltmaster latency timer register (function 1) address offset: 0dh default value: 00h attribute: read / write mlt controls the amount of time piix, as a bus master, can burst data on the pci bus. the count value is an 8-bit quantity. however, mlt[3:0] are reserved and 0 when determining the count value. mlt is cleared and suspended when piix/piix3 is not asserting frame#. when piix/piix3 asserts frame#, the counter begins counting. if the piix/piix3 finishes its transaction before the count expires, the mlt count is ignored. if the count expires before the transaction completes (count = # of clo cks programmed in mlt), piix/piix3 initiates a transaction termination as soon as its phlda# is removed. the number of clo cks programmed in the mlt represents the guaranteed time slice (measured in pci clo cks) allotted to piix. the default value of mlt is 00h or 0 pci clocks.
82371fb (piix) and 82371sb (piix3) e 50 bit description 7:4 master latency timer count value. piix-initiated pci burst cycles can last indefinitely, as long as phlda# remains active. however, if phlda# is negated after the burst cycle is initiated, piix/piix3 limits the burst cycle to the number of pci bus clocks specified by this field. 3:0 reserved 2.3.8. hedt header type register (function 1) address offset: 0eh default value: 00h attribute: read only the hedt register identifies the piix/piix3 as a multi-function device. bit description 7:0 device type (devicet). 00. multi-function device capability for piix/piix3 is defined by the hedt register in function 0. 2.3.9. bmibabus master interface base address register (function 1) address offset: 20 C23h default value: 00000001h attribute: read/write this register selects the base address of a 16 byte i/o space to provide a software interface to the bus master functions. only 12 bytes are actually used (6 bytes for primary and 6 bytes for secondary). bit description 31:16 reserved. hardwired to 0. 15:4 bus master interface base address. these bits provide the base address for the bus master interface registers and correspond to ad[15:4]. 3:2 reserved. hardwired to 0. 1 reserved. 0 resource type indicator (rte) ro. this bit is hardwired to 1 indicating that the base address field in this register maps to i/o space.
e 82371fb (piix) and 82371sb (piix3) 51 2.3.10. idetim ide timing register (function 1) address offset: primary channel=40 C41h; secondary channel=42C43h default value: 0000h attribute: read / write only this register controls the piix's ide interface and selects the timing characteristics of the pci local bus ide cycle. note that primary and secondary denotations distiguish between the cables and the 0/1 denotations distiguish between master (0) and slave (1). bit description 15 ide decode enable (ide). 1=enable; 0=disable. when enabled, i/o transactions on pci targeting the ide ata register blocks (command block and control block) are positively decoded on pci and driven on the ide interface. when disabled, these accesses are subtractively decoded to isa. 14 piix: reserved. piix3: slave ide timing register enable (sitre). 1=enable sidetim register. 0=disable (default) sidetim register. when enabled, the isp and rtc values can be programmed uniquely for each master through the fields in this register and these values can be programmed for each slave through the sidetim register. when disabled, the isp and rtc values programmed in this register apply to both master and slave drives on each channel. 13:12 iordy sample point (isp). this field selects the number of clocks between diox# assertion and the first iordy sample point. bits[13:12] number of clocks 00 5 01 4 10 3 11 2 11:10 reserved 9:8 recovery time (rtc). this field selects the minimum number of clocks between the last iordy# sample point and the diox# strobe of the next cycle. bits[9:8] number of clocks 00 4 01 3 10 2 11 1 7 dma timing enable only (dte1). when dte1=1, fast timing mode is enabled for dma data transfers for drive 1. note that pio transfers to the ide data port still run in compatible timing. 6 prefetch and posting enable (ppe1). when ppe1=1, prefetch and posting to the ide data port is enabled for drive 1. 5 iordy sample point enable drive select 1 (ie1). when ie1=0, iordy sampling is disabled for drive 1. the internal iordy signal is forced asserted guaranteeing that iordy is sampled asserted at the first sample point as specified by the isp field in this register. when ie1=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is drive 0, all accesses to the enabled i/o address range sample iordy. the iordy sample point is specified by the isp field in this register.
82371fb (piix) and 82371sb (piix3) e 52 bit description 4 fast timing bank drive select 1 (time1). when time1=0, accesses to the data port of the enabled i/o address range use the 16-bit compatible timing pci local bus path. when time1=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is drive 1, accesses to the data port of the enabled i/o address range use the fast timing bank pci local bus ide path. accesses to the data port use fast timing only if bit 7 of this register (dte1) is zero. accesses to all non-data ports of the enabled i/o address range use the 8-bit compatible timing pci local bus path. 3 dma timing enable only (dte0). when dte0=1, fast timing mode is enabled for dma data transfers for drive 0. note that pio transfers to the ide data port still run in compatible timing. 2 prefetch and posting enable (ppe0). 1=enable; 0=disable. when enabled, prefetch and posting to the ide data port is enabled for drive 0. 1 iordy sample point enable drive select 0 (ie0). when ie0=0, iordy sampling is disabled for drive 0. the internal iordy signal is forced asserted guaranteeing that iordy is sampled asserted at the first sample point as specified by the isp field in this register. when ie0=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is drive 0, all accesses to the enabled i/o address range sample iordy. the iordy sample point is specified by the isp field in this register. 0 fast timing bank drive select 0 (time0). when time0=0, accesses to the data port of the enabled i/o address range uses the 16-bit compatible timing pci local bus path. when time0=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is drive 0, accesses to the data port of the enabled i/o address range use the fast timing bank pci local bus ide path. accesses to the data port use fast timing only if bit 3 of this register (dte0) is 0. accesses to all non-data ports of the enabled i/o address range use the 8-bit compatible timing pci local bus path. 2.3.11. sidetim slave ide timing register (function 1) (piix3 only) address offset: 44h default value: 00h attribute: read / write only this register controls the piix3's ide interface and selects the timing characteristics for the slave drives on each ide channel. this allows for programming of independent operating modes for each ide agent. this register has no affect unless the sitre bit is enabled in the idetim register. bit description 7:6 secondary drive 1 iordy sample point (sisp1). this field selects the number of clocks between diox# assertion and the first iordy sample point for the slave drive on the secondary channel. bits[7:6] number of clocks 00 5 01 4 10 3 11 2
e 82371fb (piix) and 82371sb (piix3) 53 bit description 5:4 secondary drive 1 recovery time (srtc1). this field selects the minimum number of clocks between the last iordy# sample point and the diox# strobe of the next cycle for the slave drive on the secondary channel. bits[5:4] number of clocks 00 4 01 3 10 2 11 1 3:2 primary drive 1 iordy sample point (pisp1). this field selects the number of clocks between diox# assertion and the first iordy sample point for the slave drive on the primary channel. bits[3:2] number of clocks 00 5 01 4 10 3 11 2 1:0 primary drive 1 recovery time (prtc1). this field selects the minimum number of clocks between the last iordy# sample point and the diox# strobe of the next cycle for the slave drive on the primary channel. bits[1:0] number of clocks 00 4 01 3 10 2 11 1 2.4. pci configuration registers ? universal serial bus (function 2) (piix3 only) 2.4.1. vid vendor identification register (function 2) (piix3) address offset: 00 C01h default value: 8086h attribute: read only the vid register contains the vendor identification number. this register, along with the device identification register, uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification number. this is a 16-bit value assigned to intel.
82371fb (piix) and 82371sb (piix3) e 54 2.4.2. did ? device identification register (function 2) (piix3) address offset: 02 - 03h default value: 7020h attribute: read only the did register contains the device identification number. this register, along with the vid register, define the piix. writes to this register have no effect. bit description 15:0 device identification number. this is a 16-bit value assigned to the piix3. 2.4.3. pcicmd ? command register (function 2) (piix3) address offset: 04 - 05h default value: 00h attribute: read/write this register controls access to the i/o space registers. bit description 15:10 reserved. read 0. 9 fast back to back enable (fbe). (not implemented) this bit is hardwired to 0. 8:5 reserved. read as 0. 4 memory write and invalidate enable (mwi). (not implemented) this bit is hardwired to 0. 3 special cycle enable (sce). (not implemented) this bit is hardwired to 0. 2 bus master enable (bme). this bit controls the piix3s ability to act as a master on the pci bus for the host controller transfers. a value of 0 disables the device from generating pci accesses. a value of 1 allows the device to behave as a usb host controller bus master. this bit must be set to 1 before serial bus transactions can start. 1 memory space enable (mse). (not implemented) this bit is hardwired to 0. 0 i/o space enable (iose). 1=enable. 0=disable. this bit controls the access to the i/o space registers. if this bit is set, access to the host controller io registers is enabled. the base register for the i/o registers must be programmed before this bit is set.
e 82371fb (piix) and 82371sb (piix3) 55 2.4.4. ds ? device status register (function 2) (piix3) address offset: 06 - 07h default value: 0280h attribute: read/write dsr is a 16-bit status register that reports the occurrence of a pci master-abort by the usb hc module or a pci target-abort when the serial bus module is a master. the register also indicates the usb hc module devsel# signal timing that is hardwired in the usb hc module. the ds fields are shown in the table below. bit description 15 detected parity error (perr). (not implemented) read as 0. 14 serr# status (serrs). (not implemented) read as 0. 13 master-abort status (mas) ? r/wc: . when the serial bus module generates a master-abort, ma is set to a 1. software sets ma to 0 by writing a 1 to this bit. 12 received target-abort status (rta) ? r/wc. when the serial bus module is a master on the pci bus and receives a target-abort, this bit is set to a 1. software resets rta to 0 by writing a 1 to this bit. 11 signaled target-abort status (sta) ? r/wc. this bit is set when the serial bus module function is targeted with a transaction that the serial bus module terminates with a target abort. software resets sta to 0 by writing a 1 to this bit. 10:9 devsel# timing status (devt) ? ro. this 2-bit field defines the timing for devsel# assertion. these read only bits indicate the piix3s devsel# timing when performing a positive decode. since the piix3 always generate the devsel# with medium timing, devt=01. this devsel# timing does not include configuration cycles. 8 data parity detected (dpd). (not implemented). read as 0. 7 fast back to back capable (fbc) ? ro. hardwired to 1. this bit indicates to the pci master that serial bus module as a target is capable of accepting fast back-to-back transactions. 6:0 reserved . read as 0's. 2.4.5. rid ? revision identification register (function 2) (piix3) address offset: 08h default value: refer to applicable specification update document attribute: read only this 8-bit register contains device stepping information. writes to this register have no effect. bit description 7:0 revision id byte. the register is hardwired to the default value during manufacturing.
82371fb (piix) and 82371sb (piix3) e 56 2.4.6. classc ? class code register (function 2) (piix3) address offset: 09 - 0bh default value: 010180h attribute: read only this register contains the device programming interface information related to the sub-class code and base class code definition for the piix3 (function 2). this register also identifies the base class code and the function sub-class in relation to the base class code. bit description 23:1 6 base class code (basec). 0ch=universal serial bus controller. 15:8 sub-class code (scc) . 03h=universal serial bus host controller.. 7:0 programming interface (pi). 00h=capable of universal serial bus operation. 2.4.7. mlt ? master latency timer register (function 2) (piix3) address offset: 0dh default value: 00h attribute: read/write mlt is an 8-bit register that controls the amount of time (in terms of pci clo cks) the usb m odule can do transactions on the pci bus. the count value is an 8-bit quantity, however mlt[3:0] are reserved and assumed to be 0 when determining the count value. mlt is used when the usb module becomes the pci bus master and is cleared and suspended when piix3 is not asserting frame#. when piix3 asserts frame#, the counter is enabled and begins counting. if the serial bus module finishes its transaction before count is expired the mlt value is ignored. if the count expires before the transaction completes, piix3 initiates a transaction termination as soon as the current transaction is completed.. the number of clocks programmed in the mlt represents the guaranteed time slice (measured in pci clo cks) allotted to piix3, after which it must surrender the bus as soon as the current transaction is completed. the default value of mlt is 00h. bit description 7:4 master latency counter value. piix3 initiated pci cycles (including multiple transactions) can last indefinitely as long as phlda# remains active. however, if phlda# is negated after a transaction is initiated, piix3 limits the duration of the transactions to the number of pci bus clocks specified by this field. 3:0 reserved.
e 82371fb (piix) and 82371sb (piix3) 57 2.4.8. hedt ? header type register (function 2) (piix3) address offset: 0eh default value: 00h attribute: read only this register identifies the serial bus module as a single function device. bit description 7:0 device type (devicet). 00. multi-function device capability for piix/piix3 is defined by the hedt register in function 0. 2.4.9. baseadd ? i/o space base address (function 2) (piix3) address offset: 20 - 23h default value: 00h attribute: read/write this register contains the base address of the usb i/o registers. bit description 31:16 reserved. hardwired to 0s. must be written as 0s. 15:5 index register base address. bits [15:5] correspond to i/o address signals ad [15:5], respectively. 4:1 reserved. read as 0. 0 resource type indicator (rte) ro. this bit is hardwired to 1 indicating that the base address field in this register maps to i/o space. 2.4.10. il ? interrupt line register (function 2) (piix3) address offset: 3ch default value: 00h attribute: read/write software programs this register with interrupt information concerning the universal serial bus. bit description 7:0 interrupt line. . the value in this register has no affect on piix3 hardware operations.
82371fb (piix) and 82371sb (piix3) e 58 2.4.11. intrp ? interrupt pin (function 2) (piix3) address offset: 3dh default value: 04h attribute: read only this register indicates which pci interrupt pin is used for the universal serial bus module interrupt. the usb interrupt is internally ored to the interrupt controller with the pirqd# signal. bit description 7:3 reserved. 2:0 serial bus module interrupt routing. this field is hardwired to 100b to select pirqd#. 2.4.12. sbrnum ? serial bus release number (function 2) (piix3) address offset: 60h default value: 00h attribute: read only this register contains the release of the universal serial bus specification with which this universal serial bus host controller module is compliant. bit description 7:0 serial bus specification release number. all other combinations are reserved. bits[7:0] release number 00h pre-release 1.0 10h release 1.0 2.4.13. mstat ? miscellaneous status register (function 2) (piix3) address offset: 6a - 6bh default value: 01h attribute: read/write this 16-bit register provides miscellaneous control and status for the usb function.. bit description 15:1 reserved 0 usb clock selection. 1=48 mhz. 0=24 mhz.
e 82371fb (piix) and 82371sb (piix3) 59 2.4.14. legsup ? legacy support register (function 2) (piix3) pci address offset: c0 - c1h default: 2000h attribute: read/write clear this register provides control and status capability for the legacy keyboard and mouse functions. bit description 15 end of a20gate pass-through status (a20pts) ? r/wc. this bit is set to 1 to indicate that the a20gate pass-through sequence has ended. software must use the enable bits to determine the exact cause of an smi#. software cleats this bit by writing a 1 to it. 14 reserved. 13 usb pirq enable (usbpirqden) ? r/w. 1=usb interrupt is routed to pirqd (default). 0=usb interrupt does not route to pirqd. this bit prevents the usb controller from generating an interrupt. note that piix3 will typically be configured to generate an smi using bit 4 of this register. default to 1 for compatibility with older usb software. 12 usb irq status (usbirqs) ? ro. piix3 sets this bit to 1 to indicate that the usb irq is active. software must use the enable bits to determine the exact cause of an smi#. writing a 1 to this bit will have no effect. software must clear the irq via the usb controller. 11 trap by 64h write status (tby64w) ? r/wc. piix3 sets this bit to 1 to indicate that a write to port 64h occurred. software must use the enable bits to determine the exact cause of an smi#. software clears this bit by writing a 1 to it. 10 trap by 64h read status (tby64r) ? r/wc. piix3 sets this bit to 1 to indicate that a read to port 64h occurred. software must use the enable bits to determine the exact cause of an smi#. software clears this bit by writing a 1 to it. 9 trap by 60h write status (tby60w) ? r/wc. piix3 sets this bit to 1 to indicate that a write to port 60h occurred. software must use the enable bits to determine the exact cause of an smi#. software clears this bit by writing a 1 to it. 8 trap by 60h read status (tby60r) ? r/wc. piix3 sets this bit to 1 to indicate that a read to port 60h occurred. software must use the enable bits to determine the exact cause of an smi#. software clears this bit by writing a 1 to it. 7 smi at end of pass-through enable (smiepte) ? r/w. 1=enable the generation of an smi when the a20gate pass-through sequence has ended. 0=disable (default). this may be required if an smi is generated by a usb interrupt in the middle of an a20gate pass-through sequence and needs to be serviced later. 6 pass-through status (pss) ? ro. 1=a20gate pass-through sequence is currently in progress. 0=not currently executing the a20gate pass-through sequence (default). this bit indicates that the host controller is executing the a20gate pass-through sequence. if software needs to reset this bit, it should set bit 5 to 0 causing the host controller to immediately end the a20gate pass-through sequence.
82371fb (piix) and 82371sb (piix3) e 60 bit description 5 a20gate pass-through enable (a20pten) ? r/w. 1=enable a20gate pass-through sequence. 0=disable (default). when enabled, the logic will pass-through the following a20gate command sequence: cycle address data write 64h d1h ( 1 or more) (starts the sequence) write 60h xxh read 64h n/a ( 0 or more) write 64h ffh ( standard end of a20gate pass-through sequence) any deviation in the above sequence causes the host controller to immediately exit the sequence and return to standard operation, performing an i/o trap and generating an smi# if appropriate enable bits are set. when enabled, smi# is not generated during the sequence, even if the various enable bits are set. note that during a pass-through sequence, the above status bits are not set for the i/o accesses that are part of the sequence. 4 trap/smi on irq enable (usbsmien) ? r/w. 1=enable smi# generation on usb irq. 0=disable (default). 3 trap/smi on 64h write enable (64wen) ? r/w. 1=enable i/o trap and smi# generation on port 64h write. 0=disable (default). 2 trap/smi on 64h read enable (64ren) ? r/w. 1=enable i/o trap and smi# generation on port 64h read. 0=disable (default). 1 trap/smi on 60h write enable (60wen) ? r/w. 1=enable i/o trap and smi# generation on port 60h write. 0=disable (default). 0 trap/smi on 60h read enable (60ren) ? r/w. 1 = enable i/o trap and smi# generation on port 60h read. 0=disable (default).
e 82371fb (piix) and 82371sb (piix3) 61 2.5. isa-compatible registers the isa-compatible registers contain the dma, timer/counter, and interrupt registers. this group also contains the x-bus, coprocessor, nmi, and reset registers. 2.5.1. dma registers the piix/piix3 contains dma circuitry that incorporates the functionality of two 82c37 dma controllers (dma1 and dma2). the dma registers control the operation of the dma controllers and are all accessible from the host cpu via the pci bus interface. in addition, some of the registers are accessed from the isa bus via isa i/o space. unless otherwise stated, a cpurst sets each register to its default value. 2.5.1.1. dcom dma command register i/o address: channels 0-3 08h; channels 4-70d0h default value: 00h (cpurst or master clear) attribute: write only this 8-bit register controls the configuration of the dma. note that disabling channels 4-7 also disables channels 0-3, since channels 0-3 are cascaded onto channel 4. bit description 7 dack# active level (dack#[3:0, (7:5)]). 1=active high; 0=active low. 6 dreq sense assert level (dreq[3:0, (7:5)]). 1=active low; 0=active high. 5 reserved. must be 0. 4 dma group arbitration priority. 1=rotating priority; 0=fixed priority 3 reserved . must be 0 2 dma channel group enable. 1=disable; 0 = enable. 1:0 reserved . must be 0. 2.5.1.2. dcm dma channel mode register i/o address: channels 0-3=0bh; channels 4-7=0d6h default value: bits[7:2]=0; bits[1:0]=undefined (cpurst or master clear) attribute: write only each channel has a 6-bit dma channel mode register. the channel mode registers provide control over dma transfer type, transfer mode, address increment/decrement, and autoinitialization. bit description 7:6 dma transfer mode. each dma channel can be programmed in one of four different modes: bits[7:6] transfer mode 00 demand mode 01 single mode 10 block mode 11 cascade mode
82371fb (piix) and 82371sb (piix3) e 62 bit description 5 address increment/decrement select. 0=increment; 1=decrement. 4 autoinitialize enable. 1=enable; 0=disable. 3:2 dma transfer type. when bits [7:6]=11, the transfer type bits are irrelevant. bits[3:2] transfer type 00 verify transfer 01 write transfer 10 read transfer 11 illegal 1:0 dma channel select. bits [1:0] select the dma channel mode register written to by bits [7:2]. bits[1:0] channel 00 channel 0 (4) 01 channel 1 (5) 10 channel 2 (6) 11 channel 3 (7) 2.5.1.3. dr dma request register i/o address: channels 0-3 09h; channels 4-70d2h default value: bits[1:0]=undefined; bits[7:2]=0 (cpurst or master clear) attribute: write only the request register is used by software to initiate a dma request. the dma responds to the software request as though dreqx is asserted. these requests are non-maskable and subject to prioritization by the priority encoder network. for a software request, the channel must be in block mode. the request register status for dma1 and dma2 is output on bits [7:4] of a status register read. bit description 7:3 reserved . must be 0 2 dma channel service request. 0=resets the individual software dma channel request bit. 1=sets the request bit. generation of a tc also sets this bit to 0. 1:0 dma channel select. bits [1:0] select the dma channel mode register to program with bit 2. bits[1:0] channel 00 channel 0 01 channel 1 (5) 10 channel 2 (6) 11 channel 3 (7)
e 82371fb (piix) and 82371sb (piix3) 63 2.5.1.4. mask register write single mask bit i/o address: channels 0-3 0ah; channels 4-70d4h default value: bits[1:0]=undefined; bit 2=1; bits[7:3]=0 (cpurst or a master clear) attribute: write only a channel's mask bit is automatically set when the current byte/word count register reaches terminal count (unless the channel is programmed for autoinitialization). setting the entire register disables all dma requests until a clear mask register instruction allows them to occur. this instruction format is similar to the format used with the dma request register. masking dma channel 4 (dma controller 2, channel 0) also masks dma channels [3:0]. bit description 7:3 reserved . must be 0. 2 channel mask select. 1=disable dreq for the selected channel. 0=enable dreq for the selected channel. 1:0 dma channel select. bits [1:0] select the dma channel mode register for bit 2. bits[1:0] channel 00 channel 0 (4) 01 channel 1 (5) 10 channel 2 (6) 11 channel 3 (7) 2.5.1.5. mask register write all mask bits i/o address: channels 0-3 0fh; channels 4-70deh default value: bit[3:0]=1; bit[7:4]=0 (cpurst or master clear) attribute: read/write a channel's mask bit is automatically set to 1 when the current byte/word count register reaches terminal count (unless the channel is programmed for autoinitialization). setting bits [3:0] to 1 disables all dma requests until a clear mask register instruction enables the requests. note that, masking dma channel 4 (dma controller 2, channel 0), ma sks dma c hannels [3:0]. also note that, masking dma controller 2 with a write to port 0deh also masks dreq assertions from dma controller 1. bit description 7:4 reserved . must be 0. 3:0 channel mask bits. 1=disable the corresponding dreq(s); 0=enable the corresponding dreq(s). bit channel 0 0 (4) 1 1 (5) 2 2 (6) 3 3 (7)
82371fb (piix) and 82371sb (piix3) e 64 2.5.1.6. ds dma status register i/o address: channels 0-3 08h; channels 4-70d0h default value: 00h attribute: read only each dma controller has a read-only dma status register that indicates which channels have reached terminal count and which channels have a pending dma request. bit description 7:4 channel request status. when a valid dma request is pending for a channel (on its dreq signal line), the corresponding bit is set to 1. when a dma request is not pending for a particular channel, the corresponding bit is set to 0. the source of the dreq may be hardware or a software request. note that channel 4 does not have dreq or dack lines, so the response for a read of dma2 status for channel 4 is irrelevant. bit channel 40 5 1 (5) 6 2 (6) 7 3 (7) 3:0 channel terminal count status. 1=tc is reached; 0=tc is not reached. bit channel 00 1 1 (5) 2 2 (6) 3 3 (7) 2.5.1.7. dma base and current address registers (8237 compatible segment) i/o address: dma channel 0000h dma channel 40c0h dma channel 1002h dma channel 50c4h dma channel 2004h dma channel 60c8h dma channel 3006h dma channel 70cch default value: xxxxh (cpurst or master clear) attribute: read/write this register works in conjunction with the low page register. after an autoinitialization, this register retains the original programmed value. autoinitialize takes place after a tc. the address register is automatically incremented or decremented after each transfer. this register is read/written in successive 8-bit bytes. the programmer must issue the "clear byte pointer flip-flop" command to reset the internal byte pointer and correctly align the write prior to programming the current address register. autoinitialize takes place only after a tc. bit description 15:0 base and current address [15:0]. these bits represent address bits [15:0] used when forming the 24-bit address for dma transfers.
e 82371fb (piix) and 82371sb (piix3) 65 2.5.1.8. dma base and current byte/word count registers (compatible segment) i/o address: dma channel 0 001h dma channel 40c2h dma channel 1003h dma channel 50c6h dma channel 2005h dma channel 60cah dma channel 3007h dma channel 70ceh default value: xxxxh (cpurst or master clear) attribute: read/write this register determines the number of transfers to be performed. the actual number of transfers is one more than the number programmed in the current byte/word count register when the value in the register is decremented from zero to ffffh, a tc is generated. autoinitialize can only occur when a tc occurs. if it is not autoinitialized, this register has a count of ffffh after tc. for transfers to/from an 8-bit i/o, the byte/word count indicates the number of bytes to be transferred. this applies to dma channels 0-3. for transfers to/from a 16-bit i/o, with shifted address, the byte/word count indicates the number of 16-bit words to be transferred. this applies to dma channels 5-7. bit description 15:0 base and current byte/ word count. these bits represent the 16 byte/word count bits used when counting down a dma transfer. 2.5.1.9. dma memory low page registers i/o address: dma channel 0087h dma channel 508bh dma channel 1083h dma channel 6089h dma channel 2081h dma channel 708ah dma channel 3082h default value: xxh (cpurst or master clear) attribute: read/write this register works in conjunction with the current address register. after an autoinitialization, this register retains the original programmed value. autoinitialize takes place after a tc. bit description 7:0 dma low page [23:16]. these bits represent address bits [23:16] of the 24-bit dma address
82371fb (piix) and 82371sb (piix3) e 66 2.5.1.10. dma clear byte pointer register i/o address: channels 0-3 00ch; channels 4-70d8h default value: all bits undefined attribute: write only writing to this register executes the clear byte pointer command. this command is executed prior to reading/writing a new address or word count to the dma. the command initializes the byte pointer flip- flop to a known state so that subsequent accesses to register contents address upper and lower bytes in the correct sequence. the clear byte pointer command (or cpurst or the master clear command) clears the internal latch used to address the upper or lower byte of the 16-bit address and word count registers. bit description 7:0 clear byte pointer. no specific pattern. command enabled with a write to the i/o port address. 2.5.1.11. dmc dma master clear register i/o address: channel 0-3 00dh; channel 4-70dah default value: all bits undefined attribute: write only this software instruction has the same effect as the hardware reset. bit description 7:0 master clear. no specific pattern. command enabled with a write to the i/o port address 2.5.1.12. dclm dma clear mask register i/o address: channel 0-3 00eh; channel 4-70dch default value: all bits undefined attribute: write only this command clears the mask bits of all four channels, enabling them to accept dma requests. bit description 7:0 clear mask register. no specific pattern. command enabled with a write to the i/o port address. 2.5.2. timer/counter register description 2.5.2.1. tcw timer control word register i/o address: 043h default value: all bits undefined attribute: write only the timer control word register specifies the counter selection, the operating mode, the counter byte programming order and size of the count value, and whether the counter counts down in a 16-bit or binary-
e 82371fb (piix) and 82371sb (piix3) 67 coded decimal (bcd) format. after writing the control word, a new count can be written at any time. the new value takes effect according to the programmed mode. bit description 7:6 counter select. the read back command is selected when bits[7:6] are both 1. bit[7:6] function 00 counter 0 select 01 counter 1 select 10 counter 2 select 11 read back command 5:4 read/write select. the counter latch command is selected when bits[5:4] are both 0. bit[5:4] function 00 counter latch command 01 r/w least significant byte 10 r/w most significant byte 11 r/w lsb then msb 3:1 counter mode selection. bits [3:1] select one of six possible counter modes. bit[3:1] mode function 000 0 out signal on end of count (=0) 001 1 hardware retriggerable one-shot x10 2 rate generator (divide by n counter) x11 3 square wave output 100 4 software triggered strobe 101 5 hardware triggered strobe 0 binary/bcd countdown select. 0=binary countdown. the largest possible binary count is 2 16 . 1=bbinary coded decimal (bcd) count is used. the largest bcd count allowed is 10 4 . read back command the read back command is used to determine the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. the read back command is written to the timer control word register which latches the current states of the above mentioned variables. the value of the counter and its status may then be read by i/o access to the counter address. note that the timer counter register bit definitions are different during the read back command than for a normal timer counter register write. bit description 7:6 read back command. when bits[7:6]=11, the read back command is selected during a write to the timer control word register. following the read back command, i/o reads from the selected counter's i/o addresses produce the current latch status, the current latched count, or both if bits 4 and 5 are both 0. 5 latch count of selected counters. when bit 5=0, the current count value of the selected counters will be latched. when bit 5=1, the count will not be latched. 4 latch status of selected counters. when bit 4=0, the status of the selected counters will be latched. when bit 4=1, the status will not be latched. the status byte format is described in section 4.3.3, interval timer status byte format register.
82371fb (piix) and 82371sb (piix3) e 68 bit description 3 counter 2 select. when bit 3=1, counter 2 is selected for the latch command selected with bits 4 and 5. when bit 3=0, status and/or count will not be latched. 2 counter 1 select. when bit 2=1, counter 1 is selected for the latch command selected with bits 4 and 5. when bit 2=0, status and/or count will not be latched. 1 counter 0 select. when bit 1=1, counter 0 is selected for the latch command selected with bits 4 and 5. when bit 1=0, status and/or count will not be latched. 0 reserved . must be 0. counter latch command the counter latch command latches the current count value at the time the command is received. if a counter is latched once and then, some time later, latched again before the count is read, the second counter latch command is ignored. the count read will be the count at the time the first counter latch command was issued. if the counter is programmed for two byte counts, two bytes must be read. the two bytes do not have to be read successively (read, write, or programming operations for other counters may be inserted between the reads). note that the timer counter register bit definitions are different during the counter latch command than for a normal timer counter register write. note that, if a counter is programmed to read/write two-byte counts, a program must not transfer control between reading the first and second byte to another routine that also reads from that same counter. otherwise, an incorrect count will be read. bit description 7:6 counter selection. bits 6 and 7 are used to select the counter for latching. bit[7:6] function 00 latch counter 0 select 01 latch counter 1 select 10 latch counter 2 select 11 read back command select 5:4 counter latch command. when bits[5:4]=00, the counter latch command is selected during a write to the timer control word register. following the counter latch command, i/o reads from the selected counter's i/o addresses produce the current latched count. 3:0 reserved . must be 0. 2.5.2.2. interval timer status byte format register i/o address: counter 0 040h; counter 1041h; counter 2042h default value: bits[6:0]=x; bit 7=0 attribute: read only each counter's status byte can be read following an interval timer read back command. if latch status is chosen (bit 4=0, read back command) as a read back option for a given counter, the next read from the counter's counter access ports register returns the status byte. bit description 7 counter out pin state. 1=pin is 1; 0=pin is 0.
e 82371fb (piix) and 82371sb (piix3) 69 bit description 6 count register status. this bit indicates when the last count written to the count register (cr) has been loaded into the counting element (ce). 0=count has been transferred from cr to ce and is available for reading. 1=count has not been transferred from cr to ce and is not yet available for reading. 5:4 read/write selection status. bits[5:4] reflect the read/write selection made through bits[5:4] of the control register. bit[5:4] function 00 counter latch command 01 r/w least significant byte (lsb) 10 r/w most significant byte (msb) 11 r/w lsb then msb 3:1 mode selection status. bits[3:1] return the counter mode programming. bit[3:1] mode selected bit[3:1] mode selected 000 0 x11 3 001 1 100 4 x10 2 101 5 0 countdown type status. 0=binary countdown; 1=binary coded decimal (bcd) countdown. 2.5.2.3. counter access ports register i/o address: counter 0 040h; counter 1041h; counter 2042h default value: all bits undefined attribute: read/write each of these i/o ports is used for writing count values to the count registers; reading the current count value from the counter by either an i/o read, after a counter-latch command, or after a read back command; and reading the status byte following a read back command. bit description 7:0 counter port bit[x] . each counter i/o port address is used to program the 16-bit count register. the order of programming, either lsb only, msb only, or lsb then msb, is defined with the interval counter control register. the counter i/o port is also used to read the current count from the count register and return counter programming status following a read back command. 2.5.3. interrupt controller registers the piix/piix3 contains an isa-compatible interrupt controller that incorporates the functionality of two 82c59 interrupt controllers. the interrupt registers control the operation of the interrupt controller.
82371fb (piix) and 82371sb (piix3) e 70 2.5.3.1. icw1 initialization command word 1 register i/o address: int cntrl-1 020h; int cntrl-20a0h default value: all bits undefined attribute: write only a write to initialization command word 1 starts the interrupt controller initialization sequence. addresses 020h and 0a0h are referred to as the base addresses of cntrl-1 and cntrl-2, respectively. an i/o write to the cntrl-1 or cntrl-2 base address with bit 4 equal to 1 is interpreted as icw1. for piix-based isa systems, three i/o writes to "base address + 1" must follow the icw1. the first write to "base address + 1" performs icw2, the second write performs icw3, and the third write performs icw4. icw1 starts the initialization sequence during which the following automatically occur: 1. the interrupt mask register is cleared. 2. irq7 input is assigned priority 7. 3. the slave mode address is set to 7. 4. special mask mode is cleared and status read is set to irr. 5. if ic4 was set to 0, then all functions selected by icw4 are set to 0. however, icw4 must be programmed in the piix/piix3 implementation of this interrupt controller, and ic4 must be set to a 1. bit description 7:5 icw/ocw select. these bits should be 000 when programming the piix. 4 icw/ocw select. bit 4 must be a 1 to select icw1. after the fixed initialization sequence to icw1, icw2, icw3, and icw4, the controller base address is used to write to ocw2 and ocw3. bit 4 is a 0 on writes to these registers. a 1 on this bit at any time will force the interrupt controller to interpret the write as an icw1. the controller will then expect to see icw2, icw3, and icw4. 3 edge/level bank select (ltim). this bit is disabled. its function is replaced by the edge/level triggered control (elcr) registers. 2 adi. ignored for the piix. 1 single or cascade (sngl). this bit must be programmed to a 0. 0 icw4 write required (ic4). this bit must be set to a 1. 2.5.3.2. icw2 initialization command word 2 register i/o address: int cntrl-1 021h; int cntrl-20a1h default value: all bits undefined attribute: write only icw2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. bit description 7:3 interrupt vector base address. bits [7:3] define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input. 2:0 interrupt request level. must be programmed to all 0s.
e 82371fb (piix) and 82371sb (piix3) 71 2.5.3.3. icw3 initialization command word 3 register i/o address: int cntrl-1 021h default value: all bits undefined attribute: write only the meaning of icw3 differs between cntrl-1 and cntrl-2. on cntrl-1, the master controller, icw3 indicates which cntrl-1 irq line physically connects the intr output of cntrl-2 to cntrl-1. bit description 7:3 reserved. must be programmed to all 0s. 2 cascaded mode enable. this bit must be programmed to 1 selecting cascade mode. 1:0 reserved. must be programmed to all 0s. 2.5.3.4. icw3 initialization command word 3 register i/o address: int cntrl-2 0a1h default value: all bits undefined attribute: write only on cntrl-2 (the slave controller), icw3 is the slave identification code broadcast by cntrl-1. bit description 7:3 reserved. must be programmed to all 0s. 2:0 slave identification code. must be programmed to 010b. 2.5.3.5. icw4 initialization command word 4 register i/o address: int cntrl-1 021h; int cntrl-20a1h default value: 01h attribute: write only both piix/piix3 interrupt controllers must have icw4 programmed as part of their initialization sequence. bit description 7:5 reserved. must be programmed to all 0s. 4 special fully nested mode (sfnm). bit 4, sfnm, should normally be disabled by writing a 0 to this bit. if sfnm=1, the special fully nested mode is programmed. 3 buffered mode (buf). must be programmed to 0 selecting non-buffered mode. 2 master/slave in buffered mode. should always be programmed to 0. bit not used. 1 aeoi (automatic end of interrupt). this bit should normally be programmed to 0. this is the normal end of interrupt. if this bit is 1, the automatic end of interrupt mode is programmed. 0 microprocessor mode. must be programmed to 1 indicating an intel architecture-based system.
82371fb (piix) and 82371sb (piix3) e 72 2.5.3.6. ocw1 operational control word 1 register i/o address: int cntrl-1 021h; int cntrl-20a1h default value: 00h attribute: read/write ocw1 sets and clears the mask bits in the interrupt mask register (imr). each interrupt request line may be selectively masked or unmasked any time after initialization. the imr stores the interrupt line mask bits. the imr operates on the irr. masking of a higher priority input does not affect the interrupt request lines of lower priority. unlike status reads of the isr and irr, for reading the imr, no ocw3 is needed. the output data bus contains the imr when an i/o read is active and the i/o address is 021h or 0a1h (ocw1). all writes to ocw1 must occur following the icw1-icw4 initialization sequence, since the same i/o ports are used for ocw1, icw2, icw3 and icw4. bit description 7:0 interrupt request mask (mask [7:0]) . when a 1 is written to any bit in this register, the corresponding irqx line is masked. for example, if bit 4 is set to a 1, then irq4 is masked. interrupt requests on irq4 do not set channel 4's interrupt request register (irr) bit as long is the channel is masked. when a 0 is written to any bit in this register, the corresponding irqx is unmasked. note that masking irq2 on cntrl-1 also masks the interrupt requests from cntrl-2, which is physically cascaded to irq2. 2.5.3.7. ocw2 operational control word 2 register i/o address: int cntrl-1 020h; int cntrl-20a0h default value: bit[4:0]=undefined; bit[7:5]=001 attribute: write only ocw2 controls both the rotate mode and the end of interrupt mode. following a cpurst or icw initialization, the controller enters the fully nested mode of operation. both rotation mode and specific eoi mode are disabled following initialization. bit description 7:5 rotate and eoi codes. r, sl, eoi - these three bits control the rotate and end of interrupt modes and combinations of the two. a chart of these combinations is listed above under the bit definition. bits[7:5] function bits[7:5] function 001 non-specific eoi cmd 000 rotate in auto eoi mode (clear) 011 specific eoi cmd 111 *rotate on specific eoi cmd 101 rotate on non-specific eoi cmd 110 *set priority cmd 100 rotate in auto eoi mode (set) 010 no operation * l0 - l2 are used 4:3 ocw2 select. must be programmed to 00 selecting ocw2.
e 82371fb (piix) and 82371sb (piix3) 73 bit description 2:0 interrupt level select (l2, l1, l0). l2, l1, and l0 determine the interrupt level acted upon when the sl bit is active (bit 6). when the sl bit is inactive, bits [2:0] do not have a defined function; programming l2, l1 and l0 to 0 is sufficient in this case. bit[2:0] interrupt level bit[2:0] interrupt level 000 irq 0(8) 100 irq 4(12) 001 irq 1(9) 101 irq 5(13) 010 irq 2(10) 110 irq 6(14) 011 irq 3(11) 111 irq 7(15) 2.5.3.8. ocw3 operational control word 3 register i/o address: int cntrl-1 020h; int cntrl-20a0h default value: bit[6,0]=0; bit[7,4:2]=undefined; bit[5,1]=1 attribute: read/write ocw3 serves three important functionsenable special mask mode, poll mode control, and irr/isr register read control. bit description 7 reserved . must be 0. 6 special mask mode (smm). if esmm=1 and smm=1, the interrupt controller enters special mask mode. if esmm=1 and smm=0, the interrupt controller is in normal mask mode. when esmm=0, smm has no effect. 5 enable special mask mode (esmm). 1=enable smm bit; 0=disable smm bit. 4:3 ocw3 select. must be programmed to 01 selecting ocw3. 2 poll mode command. 0=disable poll mode command. when bit 2=1, the next i/o read to the interrupt controller is treated as an interrupt acknowledge cycle indicating highest priority request.. 1:0 register read command. bits [1:0] provide control for reading the in-service register (isr) and the interrupt request register (irr). when bit 1=0, bit 0 doesl not affect the register read selection. when bit 1=1, bit 0 selects the register status returned following an ocw3 read. if bit 0=0, the irr will be read. if bit 0=1, the isr will be read. following icw initialization, the default ocw3 port address read will be "read irr". to retain the current selection (read isr or read irr), always write a 0 to bit 1 when programming this register. the selected register can be read repeatedly without reprogramming ocw3. to select a new status register, ocw3 must be reprogrammed prior to attempting the read. bit[1:0] function 00 no action 01 no action 10 read irq register 11 read is register
82371fb (piix) and 82371sb (piix3) e 74 2.5.3.9. elcr1 edge/level triggered register i/o address: int cntrl-1 4d0h default value: 00h attribute: read/write elcr1 register allows irq3 - irq7 to be edge or level programmable on an interrupt by interrupt basis. irq0, irq1 and irq2 are not programmable and are always edge sensitive. bit description 7 irq7 ecl. 0 = edge triggered mode; 1 = level sensitive mode. 6 irq6 ecl. 0 = edge triggered mode; 1 = level sensitive mode. 5 irq5 ecl. 0 = edge triggered mode; 1 = level sensitive mode. 4 irq4 ecl. 0 = edge triggered mode; 1 = level sensitive mode. 3 irq3 ecl. 0 = edge triggered mode; 1 = level sensitive mode. 2:0 reserved. must be 0. 2.5.3.10. elcr2 edge/level triggered register i/o address: int cntrl-2 4d1h default value: 00h attribute: read/write elcr2 register allows irq[15,14,12:9] to be edge or level programmable on an interrupt by interrupt basis. note that, irq[13,8#] are not programmable and are always edge sensitive. bit description 7 irq15 ecl. 0 = edge triggered mode; 1 = level sensitive mode. 6 irq14 ecl. 0 = edge triggered mode; 1 = level sensitive mode. 5 reserved. must be 0. 4 irq12 ecl. 0 = edge triggered mode; 1 = level sensitive mode. 3 irq11 ecl. 0 = edge triggered mode; 1 = level sensitive mode. 2 irq10 ecl. 0 = edge triggered mode; 1 = level sensitive mode. 1 irq9 ecl. 0 = edge triggered mode; 1 = level sensitive mode. 0 reserved. must be 0.
e 82371fb (piix) and 82371sb (piix3) 75 2.5.4. x-bus, coprocessor, and reset registers 2.5.4.1. reset x-bus irq12 and irq1 register i/o address: 60h default value: n/a attribute: read only this register clears the mouse interrupt function and the keyboard interrupt (irq1). reads to this address are monitored by the piix. when the mouse interrupt function is enabled (x-bus chip select register), the mouse interrupt function is provided on the irq12/m input signal. in this mode, a mouse interrupt generates an interrupt through irq12 to the host cpu. a read of 60h releases irq12. reads/writes flow through to the isa bus. bit description 7:0 reset irq12 and irq1. no specific pattern. a read of address 60h executes the command. 2.5.4.2. coprocessor error register i/o address: f0h default value: n/a attribute: write only writing to this register causes the piix/piix3 to assert ignne#. the piix/piix3 also negates irq13 (internal to the piix). note, that ignne# is not asserted unless ferr# is active. reads/writes flow through to the isa bus. bit description 7:0 no special pattern required . a write to address f0h executes the command. 2.5.4.3. rc reset control register i/o address: cf9h default value: 00h attribute: read/write bits 1 and 2 in this register are used by the piix/piix3 to generate a hard reset or a soft reset. bit 2 should be cleared when writing the reset type (defined by bit 1) and then bit 2 should be set to initiate the reset. the 0 to 1 transition on bit 2 initiates the reset. for example, to initiate a soft reset via the cf9 reset control register, write 00h then 04h, then read the cf9 register. bit description 7:3 reserved 2 reset cpu (rcpu). this bit is used to initiate (transitions from 0 to 1) a hard reset (bit 1 in this register is set to 1) or a soft reset to the cpu. during a hard reset, the piix/piix3 asserts cpurst, pcirst#, and rstdrv. the piix/piix3 initiates a hard reset when this register is programmed for a hard reset or pwrok is asserted. this bit cannot be read as a 1.
82371fb (piix) and 82371sb (piix3) e 76 bit description 1 system reset (srst). this bit is used in conjunction with bit 2 in this register to initiate a hard reset. when srst =1, the piix/piix3 initiates a hard reset to the cpu when bit 2 in this register transitions from 0 to 1. when srst=0, the piix/piix3 initiates a soft reset when bit 2 in this register transitions from 0 to 1. 0 reserved 2.5.5. nmi registers the nmi logic incorporates two different 8-bit registers. the cpu reads the nmisc register to determine the nmi source (bits set to a 1). after the nmi interrupt routine processes the interrupt, software clears the nmi status bits by setting the corresponding enable/disable bit to a 1. the nmi enable and real-time clock register can mask the nmi signal and disable/enable all nmi sources. to ensure that all nmi requests are serviced, the nmi service routine software flow should be as follows: 1. nmi is detected by the processor on the rising edge of the nmi input. 2. the processor will read the status stored in port 061h to determine what sources caused the nmi. the processor may then set to 0 the register bits controlling the sources that it has determined to be active. between the time the processor reads the nmi sources and sets them to a 0, an nmi may have been generated by another source. the level of nmi will then remain active. this new nmi source will not be recognized by the processor because there was no edge on nmi. 3. the processor must then disable all nmis by setting bit 7 of port 070h to a 1 and then enable all nmis by setting bit 7 of port 070h to a 0. this will cause the nmi output to transition low then high if there are any pending nmi sources. the cpu's nmi input logic will then register a new nmi. 2.5.5.1. nmisc nmi status and control register i/o address: 061h default value: 00h attribute: read/write this register reports the status of different system com ponents, control the output of the speaker counter (counter 2), and gate the counter output that drives the spkr signal. bit description 7 serr# nmi source statusro. bit 7 is set if a system board agent (pci devices or main memory) detects a system board error and pulses the pci serr# line. this interrupt source is enabled by setting bit 2 to 0. to reset the interrupt, set bit 2 to 0 and then set it to 1. when writing to port 061h, bit 7 must be 0. 6 iochk# nmi source statusro. bit 6 is set if an expansion board asserts iochk# on the isa bus. this interrupt source is enabled by setting bit 3 to 0. to reset the interrupt, set bit 3 to 0 and then set it to 1. when writing to port 061h, bit 6 must be a 0. 5 timer counter 2 out statusro. the counter 2 out signal state is reflected in bit 5. the value on this bit following a read is the current state of the counter 2 out signal. counter 2 must be programmed following a cpurst for this bit to have a determinate value. when writing to port 061h, bit 5 must be a 0.
e 82371fb (piix) and 82371sb (piix3) 77 bit description 4 refresh cycle toggle ro. the refresh cycle toggle signal toggles from either 0 to 1 or 1 to 0 following every refresh cycle. when writing to port 061h, bit 4 must be a 0. 3 iochk# nmi enabler/w. 1=clear and disable; 0=enable iochk# nmis. 2 pci serr# enabler/w. 1=clear and disable; 0=enable. for the piix3, the serr# signal can be for a special protocol between the host-to-pci bridge and the piix3 (see mstat register description, 6b - 6ah, function 0). 1 speaker data enabler/w. 0=spkr output is 0; 1= the spkr output is the counter 2 out signal value. 0 timer counter 2 enabler/w. 0=disable; 1=enable. 2.5.5.2. nmi enable and real-time clock address register i/o address: 070h default value: bit[6:0]=undefined; bit 7=1 attribute: write only this port is shared with the real-time clock. do not modify the contents of this register without considering the effects on the state of the other bits. reads and writes to this register address flow through to the isa bus. bit description 7 nmi enable. 1=disable; 0=enable. 6:0 real time clock address. used by the real time clock on the base i/o component to address memory locations. not used for nmi enabling/disabling. 2.6. system power management registers this section describes two power management registers apms and apmc registers. these registers are located in normal i/o space and must be accessed (via the pci bus) with 8-bit accesses. 2.6.1. apmc advanced power management control port i/o address: 0b2h default value: 00h attribute: read/write this register passes data (apm commands) between the os and the smi handler. in addition, writes can generate an smi and reads can cause stpclk# to be asserted. the piix/piix3 operation is not effected by the data in this register. bit description 7:0 apm control port (apmc). writes to this register store data in the apmc register and reads return the last data written. in addition, writes generate an smi, if bit 7 of the smien register and bit 0 of the smicntl register are both is set to 1. reads cause the stpclk# signal to be asserted, if bit 1 of the smicntl register is set to 1. reads do not generate an smi.
82371fb (piix) and 82371sb (piix3) e 78 2.6.2. apms advanced power management status port i/o address: 0b3h default value: 00h attribute: read/write this register passes status information between the os and the smi handler. the piix/piix3 operation is not effected by the data in this register. bit description 7:0 apm status port (apms). writes store data in this register and reads return the last data written. 2.7. pci bus master ide registers the pci bus master ide function uses 16 bytes of i/o space, allocated via the bmiba register (a pci base address register). all bus master ide i/o space registers can be accessed as byte, word, or dword quantities. the description of the 16 bytes of i/o registers follows: 2.7.1. bmicombus master ide command register address offset: primary channel base + 00h; secondary channelbase + 08h default value: 00h attribute: read / write this register enables/disables bus master capability for the ide function and provides direction control for the ide dma transfers. this register also provides bits that software uses to indicate dma capability of the ide device. bit description 7:4 reserved 3 bus master read/write control (rwcon). 0=reads; 1=writes. this bit must not be changed when the bus master function is active. 2:1 reserved. 0 start/stop bus master (ssbm). 1=start; 0=stop. when this bit is set to 1, bus master operation starts. the controller transfers data between the ide device and memory only when this bit is set. master operation can be stopped by writing a 0 to this bit. this results in all state information being lost (i.e., master mode operation cannot be stopped and then resumed). if this bit is set to 0 while bus master operation is still active (i.e., bit 0=1 in the bus master ide status register for that ide channel) and the drive has not yet finished its data transfer (bit 2=0 in the channel's bus master ide status register), the bus master command is aborted and data transferred from the drive may be discarded before being written to system memory. this bit is intended to be set to 0 after the data transfer is completed, as indicated by either bit 0 or bit 2 being set in the ide channel's bus master ide status register.
e 82371fb (piix) and 82371sb (piix3) 79 2.7.2. bmista bus master ide status register address offset: primary channel base + 02h; secondary channelbase + 0ah default value: 00h attribute: read/write clear this register provides status information about the ide device and state of the ide dma transfer. table 8 describes ide interrupt status and bus master ide active bit states after a dma transfer has been started. bit description 7 reserved. this bit is hardwired to 0. 6 drive 1 dma capable (dma1cap) r/w. 1=drive 1 is capable of dma transfers. this bit is a software controlled status bit that indicates ide dma device capability and does not affect hardware operation. 5 drive 0 dma capable (dma0cap)r/w. 1=drive 0 is capable of dma transfers. this bit is a software controlled status bit that indicates ide dma device capability and does not affect hardware operation. 4:3 reserved. 2 ide interrupt statusr/wc. this bit, when set to a 1, indicates when an ide device has asserted its interrupt line. when bit 2=1, and bit 0=0, i.e. 100b, all read data from the ide device has been transferred to main memory and all write data has been transferred to the ide device. software sets this bit to a 0 by writing a 1 to it. irq14 is used for the primary channel and mirq0 is used for the secondary channel. irq15 is used for the secondary channel when irq0 bit, bit5 in the mirq0 register, is set. if the interrupt status bit is set to a 0 by writing a 1 to this bit while the interrupt line (irq14 or mirq0) is still at the active level, this bit remains 0 until another assertion edge is detected on the interrupt line. 1 ide dma errorr/wc. this bit is set to 1 when the piix/piix3 encounters a target abort or master abort while transferring data on the pci bus. software sets this bit to a 0 by writing a 1 to it. 0 bus master ide active (bmidea)ro. the piix/piix3 sets this bit to 1 when bit 0 in the bmicom register is set to 1. the piix/piix3 sets this bit to 0 when the last transfer for a region is performed (where eot for that region is set in the region descriptor). the piix/piix3 also sets this bit to 0 when bit 0 of the bmicom register is set to 0 or when bit 1 of this register is set to 1. when this bit is read as a zero, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. table 8. interrupt/activity status combinations bit 2 bit 0 description: 01 dma transfer is in progress. no interrupt has been generated by the ide device. 10 the ide device generated an interrupt and the physical region descriptors exhausted. this is normal completion where the size of the physical memory regions is equal to the ide device transfer size. 11 the ide device generated an interrupt. the controller has not reached the end of the physical memory regions. this is a valid completion case when the size of the physical memory regions is larger than the ide device transfer size.
82371fb (piix) and 82371sb (piix3) e 80 bit 2 bit 0 description: 00 error condition. if the ide dma error bit is 1, there is a problem transferring data to/from memory. specifics of the error have to be determined using bus-specific information. if the error bit is 0, the prd's specified a smaller size than the ide transfer size. 2.7.3. bmidtp bus master ide descriptor table pointer register address offset: primary channel base + 04h; secondary channelbase + 0ch default value: 00000000h attribute: read/write this register provides the base memory address of the descriptor table. the descriptor table must be dword aligned and not cross a 4-kbyte boundary in memory. bit description 31:2 descriptor table base address. bits [31:2] correspond to a[31:2]. 1:0 reserved. 2.8. usb i/o registers this section describes the block of usb registers that are located in normal i/o space. the base portion of the i/o address is selected via a pci configuration register. 2.8.1. usbcmd ? usb command register i/o address: base+ (00 - 01h) default value: 0000h attribute: read/write the command register indicates the command to be executed by the serial bus host/hub controller. writing to the register causes a command to be executed. bit description 15:8 reserved. 7 max packet (maxp). 1=64 bytes. 0=32 bytes. this bit selects the maximum packet size that can be used for full speed bandwidth reclamation at the end of a frame. this value is used by the host controller to determine whether it should initiate another transaction based on the time remaining in the sof counter. use of reclamation packets larger than the programmed size will cause a babble error if executed during the critical window at frame end. the babble error results in the offending endpoint being stalled. software is responsible for ensuring that any packet that could be executed under bandwidth reclamation be within this size limit. 6 configure flag (cf). software sets this bit as the last action in its process of configuring the host controller. this bit has no effect on the hardware. it is provided only as a semaphore service for software.
e 82371fb (piix) and 82371sb (piix3) 81 bit description 5 software debug (swdbg). 1=debug mode. 0=normal mode. in sw debug mode, the host controller clears the run/stop bit after the completion of each usb transaction. the next transaction is executed when software sets the run/stop bit back to 1. the swdbg bit must only be manipulated when the controller is in the stopped state. this can be determined by checking the hchalted bit in the usbsts register. 4 force global resume (fgr). 1=host controller sends the global resume signal on the usb. software sets this bit to 0 after 20 ms has elapsed to stop sending the global resume signal. at that time all usb devices should be ready for bus activity. the host controller sets this bit to 1 when a resume event (connect, disconnect, or k-state) is detected while in global suspend mode. software resets this bit to 0 to end global resume signaling. the 1 to 0 transition causes the port to send a low speed eop signal. this bit remains a 1 until the eop has completed. 3 enter global suspend mode (egsm). 1=host controller enters the global suspend mode. no usb transactions occur during this time. the host controller is able to receive resume signals from usb and interrupt the system. software resets this bit to 0 to come out of global suspend mode. software writes this bit to 0 at the same time that force global resume (bit 4) is written to 0 or after writing bit 4 to 0. software must also ensure that the run/stop bit (bit 0) is cleared prior to setting this bit. 2 global reset (greset). when this bit is set, the host controller sends the global reset signal on the serial bus and then resets all its logic, including the internal hub registers. the hub registers are reset to their power on state. this bit is reset by the software after a minimum of 10 ms has elapsed as specified in chapter 7 of the usb specification. note: chip hardware reset has the same effect as global reset (bit 2), except that the host controller does not send the global reset on usb. 1 host controller reset (hcreset). when this bit is set to a 1, the host controller module resets its internal timers, counters, state machines, etc. to their initial value. any transaction currently in progress on usb is immediately terminated. this bit is reset by the host controller when the reset process is complete. the hcreset acts on hub registers are slightly different for chip hardware reset and global usb reset. the hcreset affects bits [8,3:0] of the port status and control register (portsc) of each port. hcreset resets the state machines of the host controller including the connect/disconnect state machine (one for each port). when the connect/disconnect state machine is reset, the output that signals connect/disconnect are negated to 0, effectively signaling a disconnect, even if a device is attached to the port. this virtual disconnect causes the port to be disabled. this disconnect and disabling of the port causes bit 1 (connect status change) and bit 3 (port enable/disable change) of the portsc to get set. the disconnect also causes bit 8 of portsc to reset. about 64 bit times after hcreset goes to 0, the connect and low-speed detect will take place and bits 0 and 8 of the portsc will change accordingly. 0 run/stop (rs). 1=run. 0=stop. when set to a 1, the host controller proceeds with execution of the schedule. the host controller continues execution as long as this bit is set. when this bit is set to 0, the host controller completes the current transaction on the usb and then halts. the hc halted bit in the status register indicates when the host controller has finished the transaction and has entered the stopped state. the host controller clears this bit when the following fatal errors occur: consistency check failure, pci bus errors.
82371fb (piix) and 82371sb (piix3) e 82 table 9. run/stop, debug bit interaction swdbg (bit 5) run/stop (bit 0) operation 0 0 if executing a command, the host controller completes the command and then stops. the 1.0 ms frame counter is reset and command list execution resumes from start of frame using the frame list pointer selected by the current value in the frnum register. (while run/stop=0, the frnum register can be reprogrammed). 0 1 execution of the command list resumes from start of frame using the frame list pointer selected by the current value in the frnum register. the host controller remains running until the run/stop bit is cleared (by software or hardware). 1 0 if executing a command, the host controller completes the command and then stops and the 1.0 ms frame counter is frozen at its current value. all status are preserved. the host controller begins execution of the command list from where it left off when the run/stop bit is set. 1 1 execution of the command list resumes from where the previous execution stopped. the run/stop bit is set to 0 by the host controller when a td is being fetched. this causes the host controller to stop again after the execution of the td (single step). when the host controller has completed execution, the hc halted bit in the status register is set. 2.8.2. usbsts ? usb status register i/o address: base + (02 - 03h) default value: 0000h attribute: read/write clear size: 16 bits this register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. software sets a bit to 0 in this register by writing a 1 to it. bit description 15:6 reserved . 5 hchalted. the host controller sets this bit to 1 after it has stopped executing as a result of the run/stop bit being set to 0, either by software or by the host controller hardware (an internal error). 4 host controller process error. the host controller sets this bit to 1 when it detects a fatal error and indicates that the host controller suffered a consistency check failure while processing a transfer descriptor. an example of a consistency check failure would be finding an illegal pid field while processing the packet header portion of the transfer descriptor (td) data structure. when this error occurs, the host controller clears the run/stop bit in the command register to prevent further schedule execution. a hardware reset is generated to the system.
e 82371fb (piix) and 82371sb (piix3) 83 bit description 3 pci bus error. the host controller sets this bit to 1 when a serious error occurs during a pci access involving the host controller module. pci conditions that set this bit to 1 include pci master abort and pci target abort. when this error occurs, the host controller clears the run/stop bit in the command register to prevent further execution of the scheduled tds. a hardware reset is generated to the system. 2 resume received. the host controller sets this bit to 1 when it receives a resume signal from a usb device. this is only valid if the host controller has been in a suspended state (bit 3 of command register = 1). 1 usb error interrupt. the host controller sets this bit to 1 when completion of a usb transaction results in an error condition (e.g., error counter underflow). if the transfer descriptor (td) data structure on which the error interrupt occurred also had its ioc bit set, both this bit and bit 0 are set. 0 usb interrupt (usbint). the host controller sets this bit to 1 when the cause of an interrupt is a completion of a usb transaction whose transfer descriptor had its ioc bit set. the host controller also sets this bit to 1 when a short packet is detected (actual length field in td is less than maximum length field in td), and short packets are enabled in that td. 2.8.3. usbintr ? usb interrupt enable register i/o address: base + (04 - 05h) default value: 0000h attribute: read/write size: 16 bits this register enables/disables reporting of the corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. fatal errors (host controller processor error- bit 4, usbsts register) cannot be disabled. interrupt sources that are disabled in this register still appear in the status register to allow the software to poll for events. bit description 15:4 reserved . 3 short packet interrupt enable. 1=enabled. 0=disabled. 2 interrupt on complete (ioc) enable. 1= enabled. 0=disabled. 1 resume enable. 1= enabled. 0=disabled. 0 timeout/crc enable. 1= enabled. 0=disabled. 2.8.4. frnum ? frame number register i/o address: base + (06 - 07h) default value: 0000h attribute: read/write (writes must be word writes) size: 16 bits bits [10:0] of this register contain the current frame number and this number is included in the frame sof packet. this register reflects the count value of the internal frame number counter. bits [9:0] are used to
82371fb (piix) and 82371sb (piix3) e 84 select a particular entry in the frame list during schedule execution. (frame list is one of the data structures located in system memory that is processed by the host controller.) this register must be written as a word. byte writes are not supported. this register cannot be written unless the host controller is in the stopped state as indicated by the hchalted bit (u sbsts register). a write to this register while the run/stop bit (usbcmd register) is set is ignored. bit description 15:11 reserved. 10:0 frame list current index/frame number. bits [10:0] provide the frame number in the sof frame. the value in this register increments at the end of each time frame (approximately every 1 ms). in addition, bits [9:0] are used for the frame list current index and correspond to memory address signals [11:2]. 2.8.5. flbaseadd ? frame list base address register i/o address: base + (08 - 0bh) default value: undefined attribute: read/write size: 32 bits this 32-bit register contains the beginning address of the frame list in the system memory. software l oads this register prior to starting the schedule execution by the host controller. when written, only the upper 20 bits are used. the lower 12 bits are written as zero (4 kbyte alignment). the contents of this register are combined with the frame number counter to enable the host controller to step through the frame list in sequence. the two lsb are always 00. this requires dword alignment for all list entries. this configuration supports 1k (1024) frame list entries. note that frame list is one of the data structures located in system memory that is processed by the host controller during schedule execution. bit description 31:12 base address. these bits correspond to memory address signals [31:12], respectively. 11:0 reserved. must be written as 0s. 2.8.6. start of frame (sof) modify register i/o address: base + (0ch) default value: 40 attribute: read/write size: 8 bits this one byte register is used to modify the value used in the generation of sof timing on the usb. only the 7 least significant bits are used. when a new value is written into the these 7 bits, the sof timing of the next frame will be adjusted. this feature can be used to adjust out any offset from the frequency synthesizer that generates the clock that drives the sof counter. this register can also be used to maintain real time synchronization with the rest of the system so that all devices have the same sense of real time. using this register, the frame length can be adjusted across the full range required by the usb specification. its initial programmed value is system dependent based on the accuracy of hardware usb clock and is initialized by system bios. it may be reprogrammed by usb system software at any time. its new value will
e 82371fb (piix) and 82371sb (piix3) 85 take effect from the beginning of the next frame. this register is reset upon a host controller reset or global reset. software must maintain a copy of its value for reprogramming if necessary. bit description 7 reserved. 6:0 sof timing value. guidelines for the modification of frame time are contained in chapter 7 of the usb specification. the sof counter is initialized to a count of 11936. the sof cycle time (number of sof counter clock periods to generate a sof) is equal to 11936 + value in this field. the default value is decimal 64 which gives a sof count value of 12000. for a 12 mhz sof counter clock input, this produces a 1 ms frame period. the following table indicates what sof timing value to program into this field for a certain frame. frame length sof reg. value (# 12mhz clocks) (decimal) (decimal) 11936 0 11937 1 . . . . 11999 63 12000 64 12001 65 . . . . 12062 126 12063 127 2.8.7. portsc ? port status and control register i/o address: base + (10 - 11h) ? port 1 base + (12 - 13h) ? port 2 default: 0000h access: read/write (word writeable only) size: 16 bits after a power-up and after a reset, the initial conditions of a port are: no device connected, port disabled, and the bus line status is 00 (single-ended zero). note: if a device is attached, the port state will transition to the attached state and system software will process this as with any status c hange notification. it may take up to 64 usb bit times for the port transition to occur. note that, if the host controller is in global suspend mode, then, if any of bits [6,3,1] gets set, the host controller will signal a resume. refer to chapter 11 of the usb specification for details on hub operation.
82371fb (piix) and 82371sb (piix3) e 86 bit description 15:13 reserved. must written as 0s when writing this register. 12 suspend ? r/w. 1=port in suspend state. 0=port not in supsend state. this bit should not be written to a 1 if global suspend is active (bit 3=1 in the usbcmd register). bit 2 and bit 12 of this register define the hub states as follows: bits [12,2] hub port state x0 disable 01 enable 11 suspend when in suspend state, downstream progagation of data is blocked on this port, except for single-ended 0 resets (global reset and port reset). the blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. in the suspend state the port will respond to a resume. note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the usb. 11:10 reserved. 9 port reset ? r/w . 1=port is in reset. 0=port is not in reset. when in the reset state, the port is disabled and sends the usb reset signaling. note that host software must guarantee that the reset signaling is active for the proper amount of time as specified in the usb specification. 8 low speed device attached ? ro. 1=low speed device is attached to this port. 0=full speed device. writes have no effect. 7 reserved ? ro. always read as 1. 6 resume detect ? ro. 1= resume detected/driven on port. 0=no resume (k-state) detected/driven on port. software sets this bit to a 1 to drive resume signalling. the host controller sets this bit to a 1 if a j-to-k transition is detected while the port is in the suspend state. note that when this bit is 1, a k-state is driven on the port as long as this bit remains 1 and the port is still in suspend state. writing a 0 (from 1) causes the port to send a low speed eop. this bit remains a 1 until the eop has completed. 5:4 line status ? ro. these bits reflect the d+ (bit 4) and d- (bit 5) signals lines logical levels. these bits are used for fault detect and recovery as well as for usb diagnostics. this field is updated at eof2 time (see chapter 11 of the usb specification). 3 port enable/disable change ? r/wc. 1=port enabled/disabled status has changed. 0=no change. for the root hub, this bit gets set only when a port is disabled due to disconnect on the that port or due to the appropriate conditions existing at the eof2 point (see chapter 11 of the usb specification). software clears this bit by writing a 1 to it. 2 port enabled/disabled ? r/w. 1=enable. 0=disable. ports can be enabled by host software only. ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. note that the bit status does not change until the port state actually changes and that there may be a delay in disabling a port if there is a transaction currently in progress on the usb.
e 82371fb (piix) and 82371sb (piix3) 87 bit description 1 connect status change ? r/wc. 1=change in current connect status. 0=no change. indicates a change has occurred in the ports current connect status (see bit 0). the hub device sets this bit for any changes to the port device connect status, even if system software has not cleared a connect status change. if, for example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). however, the hub transfers the change bit only once when the host controller requests a data transfer to the status change endpoint. system software is responsible for determining state change history in such a case. software sets this bit to 0 by writing a 1 to it. 0 current connect status ? ro. 1=device is present on port. 0=no device is present. this value reflects the current state of the port, and may not correspond directly to the event that caused the insertion status change bit (bit 1) to be set. table 10 and table 11 show host controller behavior when a port receives resume, connect, or disconnect signaling and the host controller is in global suspend state or not in the global suspend state. a full explanation of hub behavior is given in chapter 11 of the usb specification. typically, the portsc register associated with the port receiving the signaling reflects the status change appropriate for the type of signaling received. resume signaling (k-state) is recognized in the portsc register only if the port is in selective suspend (portsc[bits 2,12]=1,1). resume is recognized (usbsts[bit 2]=1), if resume is received on a suspended or enabled port when the host controller is in the global suspend state (usbcmd[bit 3]=1). the host may also initiate a resume on a suspended port or when the host controller has been suspended by writing the appropriate resume-detect/force-resume bit to a 1. a global resume is started by writing usbcmd[bit 4] to a 1. a k-state signal is sent on all enabled ports. any port that needs to send the resume signal and is not enabled must be enabled before the resume is forced. a resume can be forced on a selectively suspended port by writing the corresponding portsc[bit 6] to a 1. resume signaling is ended by clearing the appropriate suspend and resume bits. this is true for either selective or global resumes, or resumes initiated by signaling at the port or by the host controller. for proper single-ended zero termination of the resume signaling, the suspend and resume bits must be simultaneously written to 0 (same write cycle) or the sus pend must be written to a 0 after the resume bit is reset. resume is ended on a suspended host controller by writing usbcmd[bits 3,4] to 0. resume is ended on a suspended port by writing portsc[bits 6,12] to 0. if signaling on a suspended port in a globally suspended host controller is the source of the resume, the host controller suspend and resume bits should be cleared before the port bits are cleared. table 10. behavior during resume when host not in global suspend state adjacent port response port status and signaling type signaled port response enabled port disabled port suspended port port disabled, resume k-state received no effect no effect no effect no effect port suspended, resume k-state received resume reflected downstream on signaled port. resume detect status bit in portsc register is set. no effect no effect no effect port enabled, disabled or suspended and disconnect received portsc connect and enable status bits are cleared, and connect change and enable/disable change status bits are set. no effect no effect no effect
82371fb (piix) and 82371sb (piix3) e 88 table 10. behavior during resume when host not in global suspend state adjacent port response port status and signaling type signaled port response enabled port disabled port suspended port port disabled and connect received portsc connect status and connect status change bits are set. no effect no effect no effect table 11. behavior during resume when host is in global suspend state adjacent port response port status and signaling type signaled port response enabled port disabled port suspended port port enabled, resume k-state received resume reflected downstream on signaled port. resume detect status bit in usbsts reg is set. signal resume downstream no effect no effect port disabled, resume k-state received no effect no effect no effect no effect port suspended, resume k-state received resume signal reflected downstream on signaled port. resume detect status bit in portsc and usbsts regs are set. signal resume downstream no effect no effect port enabled, disabled or suspended and disconnect received resume detect status bit in usbsts reg is set. portsc connect and enable status bits are cleared and connect change and enable/disable change bits are set. signal resume downstream no effect no effect port disabled and connect received resume detect status bit in usbsts reg is set. portsc connect status bit and connect change status bit are set. signal resume downstream no effect no effect
e 82371fb (piix) and 82371sb (piix3) 89 3.0. functional description this section describes each of the major functions on the piix/piix3 including the memory and i/o address map, dma controller, interrupt controller, timer/counter, and power management. the pci, isa, x-bus, and ide interfaces. 3.1. memory and i/o address map the piix/piix3 interfaces to two system buses pci and isa buses. the piix/piix3 provides positive decode for certain i/o and memory space accesses on these buses as described in this section. isa masters and dma devices have access to pci memory and some of the internal piix/piix3 registers as described in the register description section. isa masters and dma devices do not have access to host or pci i/o space. 3.1.1. i/o accesses the piix/piix3 positively decodes accesses to the pci configuration registers (pci only), power management registers (pci only), and bus master ide interface registers (pci only). the piix/piix3 subtractively decodes memory accesses to the apic registers (pci only), the piix/piix3 also positively decodes the isa-compatible registers (pci and isa), except for the dma register i/o space which is subtractively decoded. for details concerning accessing these registers, see register description section. the piix/piix3 also provides positive decode for bios, x-bus, and system event dec ode for smm support. in addition, the piix/piix3 positively decodes pci bus accesses to registers located on the ide device, when enabled. for ide port accesses, see pci local bus ide section. 3.1.2. memory address map for pci accesses to isa memory, accesses below 16 mbytes (including bios space) that are not claimed by a pci device (subtractive decode) are forwarded to isa. for write accesses that are not claimed by an isa slave, the cycle completes normally (i.e., 8-bit, 6 sysclk cycle). for r ead accesses that are not claimed by an isa slave, the piix/piix3 returns data corresponding to the state of the isa bus and completes the cycle normally (i.e., 8-bit, 6 sysclk cycle). for isa/dma accesses to main memory, all accesses to memory locations 0C512 kbytes (512C640 kbytes, if enabled), or accesses above 1 mbyte and below the top of memory are forwarded to the pci bus (table 12). the top of memory is equal to the value programmed in the top of memory register (bits [7:3]). the piix3 can also enable isa/dma accesses to the vga frame buffer space from 640-768 kbytes (a0000-bffffh). all remaining isa originated accesses are confined to the isa bus. table 12. dma and isa master accesses to main memory memory space response top of main memory to 128 mbytes confine to isa 1 mbyte to top of main memory forward to main memory 1 1 mbyte minus 128 kbytes to 1 mbyte minus 64 kbytes confine to isa 2 640 kbytes to 1 mbyte minus 128 kbytes confine to isa 512C640 kbytes confine to isa 3 0C512 kbytes forward to pci
82371fb (piix) and 82371sb (piix3) e 90 notes: 1. except accesses to programmed memory hole. 2. forward to main memory if bit 6=0 in the xbcs register and bit 3=1 in the tom register. 3. forward to main memory if bit 1=0 in the tom register. 3.1.3. bios memory the piix/piix3 supports 512 kbytes of bios space. this includes the normal 128-kbyte space plus an additional 384-kbyte bios space (known as the extended bios area). the xbcs register provides bios space access control. access to the lower 64-kbyte block of the 128-kbyte space and the extended bios space can be individually enabled/disabled. in addition, write protection can be programmed for the entire bios space. pci access to bios memory the 128-kbyte bios memory space is located at 000e0000 C000fffffh (top of 1 mbyte) and is aliased at fffe0000h (top of 4 gbytes). this 128-kbyte byte block is split into two 64-kbyte blo cks. accesses to the top 64 kbytes (000f0000C000fffffh) are forwarded to the isa bus and bioscs# is always generated. accesses to the bottom 64 kbytes (000e0000C000effffh) are forwarded to the isa bus and bioscs# is only generated when this bios region is enabled. 1.if this bios region is enabled (bit 6=1 in the xbcs register), accesses to the aliased region at the top of 4 gbytes (fffe0000h - fffeffffh) are forwarded to isa and bioscs# generated. if disabaled, these accesses are not forwarded to isa and bioscs# is not generated. the additional 384-kbyte region resides at fff80000Cfffdffffh. if this bios region is enabled (bit 7=1 in the xbcs register), these accesses (fff80000hCfffdffffh) are forwarded to isa and bioscs# generated. if disabled, these accesses are not forwarded to isa and bioscs# not generated. isa access to bios memory the piix/piix3 confines all isa-initiated bios accesses to the top 64 kbytes of the 128-kbyte region (f0000Cfffffh) to the isa bus, even if bios is shadowed in main memory. accesses to the bottom 64 kbytes of the 128-kbyte bios region (e0000Ceffffh) are confined to the isa bus, when this region is enabled. when the bios region is disabled, accesses are forwarded to main memory. accesses to the top 64-kbyte bios region always generates bioscs#. accesses to the bottom 64-kbyte bios region generate bioscs#, when this region is enabled. 3.2. pci interface the piix/piix3 incorporates a fully pci bus compatible master and slave interface. as a pci master, the piix/piix3 runs cycles on behalf of dma, isa masters, or a bus master ide. as a pci slave, the piix/piix3 accepts cycles initiated by pci masters targeted for the piix's internal register set or the isa bus. the piix/piix3 directly supports the pci interface running at either 25 mhz, 30 mhz, or 33 mhz. 3.2.1. transaction termination the piix/piix3 supports the standard pci cycle terminations as described in the pci local bus specification. piix/piix3 as master master-initiated termination: the piix/piix3 supports three forms of master- initiated termination: 1.) normal termination of a completed transaction, 2.) normal termination of an incomplete transaction due to timeout (applies to line buffer operations-ide bus master, 3.) abnormal termination due to the slave not responding to the transaction (abort).
e 82371fb (piix) and 82371sb (piix3) 91 piix/piix3 as a master response to target-initiated termination: as a master, the piix/piix3 responds in one of three ways to a target-termination ? target-abort, retry, or disconnect. piix/piix3 as a targettarget-initiated termination: the piix/piix3 supports three forms of target- initiated termination ? disconnect, retry, target abort. 3.2.2. parity support as a master, the piix/piix3 generates address parity for read/write cycles and data parity when the piix/piix3 is providing the data. as a slave, the piix/piix3 generates data parity for read cycles. the piix/piix3 does not check parity and does not generate serr#. however, the piix/piix3 does generate an nmi when another pci device asserts serr# (if enabled). par is the calculated parity signal. par is even parity and is calculated on 36 bits ad[31:0] signals plus c/be[3:0]#.par is always calculated on 36 bits, regardless of the valid byte enables. par is only guaranteed to be valid one pci clock after the corresponding address or data phase. 3.2.3. pci arbitration the piix/piix3 requests the use of the pci bus on behalf of isa devices (bus masters and dma) and ide dma slave devices using the phold# and phlda# signals. these signals connect to the host-to-pci bridge where the pci arbiter is located. isa devices (bus master or dma) assert dreq to gain access to the isa bus. in response, the piix/piix3 asserts phold#. the piix/piix3 keeps dack negated until the piix/piix3 has ownership of the pci bus and memory. the pci arbiter asserts phlda# to the piix/piix3 when the above conditions are met. the piix/piix3 gives ownership of the isa bus (pci and memory) to the isa device after sampling phlda# asserted. arbitration the piix/piix3 requests the use of pci bus on behalf of isa devices, ide masters and usbhc channels. the piix/piix3 arbitrates for the pci bus through the phold# and phlda# signals. the isa dma/master channels, the ide bus master channels and usbhc channels are arbitrated fairly as a group (fairness between three groups). multiple transactions on pci bus (piix3 only) the usb module utilizes the arbitration advantage available through the phold#/phlda# to do multiple transactions on the pci bus once it has the ownership of the bus and the mlt count has not expired. the usbhc relinquishes the bus ownership as soon the transactions are completed or the mlt counter has expired, whichever happens first. refer to the dlc register description for information on delayed completion and passive release.
82371fb (piix) and 82371sb (piix3) e 92 3.3. isa interface the piix/piix3 incorporates a fully isa bus compatible master and slave interface. the piix/piix3 directly drives five isa slots without external data buffers. external transceivers are used on the sa[19:8] and sbhe# signals to permit these signals to be used with the ide interface (figure 1). the isa interface also provides byte swap logic, i/o recovery support, wait state generation, and sysclk generation. the isa interface supports the following types of cycles: pci master-initiated i/o and memory cycles to the isa bus dma compatible cycles between main memory and isa i/o and between isa i/o and isa memory enhanced dma cycles between pci memory and isa i/o (for motherboard devices only) isa refresh cycles initiated by either the piix/piix3 or an external isa master isa master-initiated memory cycles to pci and isa master-initiated i/o cycles to the internal piix/piix3 registers, as shown in isa-compatible register table in the register description section. als245 soe#, sdir la[23:17] sa[19:8] sbhe# pcs# 051908_3.drw piix/piix3 dd[15:0] 14 bioscs#, rtccs#, kbccs# sa[7:0] sd[15:0] to ide connector isa control signals 051908 figure 1. isa interface
e 82371fb (piix) and 82371sb (piix3) 93 3.4. dma controller the dma circuitry incorporates the functionality of two 82c37 dma controllers with seven independently programmable channels (channels 0-3 and channels 5-7). dma channel 4 is used to cascade the two controllers and defaults to cascade mode in the dma channel mode (dcm) register. in addition to accepting requests from dma slaves, the dma controller also responds to requests that are initiated by software. software may initiate a dma service request by setting any bit in the dma channel request register to a 1. the dma controller for channels 0-3 is referred to as "dma-1" and the controller for channels 4-7 is referred to as "dma-2". channel 0 channel 1 channel 3 channel 2 dma-1 channel 4 channel 5 channel 7 channel 6 dma-2 051902_3.drw 051902 figure 2. internal dma controller each dma channel is hardwired to the compatible settings for dma device size; channels [3:0] are hardwired to 8-bit count-by-bytes transfers and channels [7:5] are hardwired to 16-bit count-by-words (address shifted) transfers. the piix/piix3 provides the timing control and data size translation necessary for the dma transfer between the memory (isa or main memory) and the isa bus device. isa compatible and f type dma timing are supported. type f dma is selected via the mbdma[1:0] registers and permits up to two channels to be programmed for type f transfers at the same time. the piix/piix3 provides 24-bit addressing in compliance with the isa-compatible specification. each channel includes a 16-bit isa-compatible current register that contains the 16 least-significant bits of the 24-bit address, an isa compatible page register that contains the eight next most significant bits of address. the dma controller also features refresh address generation, and auto-initialization following a dma termination. the dma controller is either in master or slave mode. in master mode, the dma controller is either servicing a dma slave's request for dma cycles or allowing a 16-bit isa master to use the bus (via a casc aded dreq signal). in slave mode, the piix/piix3 monitors both the isa bus and pci, decoding and responding to i/o read and write commands that address its registers. note that a dma device (i/o device) is always on the isa bus, but the memory referenced is located on either an isa bus device or on pci. when the piix/piix3 is running a compatible dma cycle, it drives the memr# or memw# strobes if the address is less than 16 mbytes (000000 Cffffffh). these memory strobes are generated regardless of whether the cycle is dec oded for pci or isa memory. the smemr# and smemw# are generated if the address is less than 1 mbytes (0000000C00fffffh). if the address is greater than 16 mbytes (1000000C7ffffffh), the memr# or memw# strobe is not generated in order to avoid aliasing problems. the piix/piix3 drives the aen signal asserted (high) during dma cycles to prevent the i/o devices from misinterpreting the dma cycle as a valid i/o cycle. the bale si gnal is also driven high during dma cycles. also, during dma memory read cycles to the pci bus, the piix/piix3 the data on the isa bus is considered random if the pci cycle is either target aborted or master aborted.
82371fb (piix) and 82371sb (piix3) e 94 note 1. for type f timing mode dma transfers, the channel must be programmed with a memory range that will be forwarded to pci. this means that if bios detects that isa memory is used in the system (i.e., that the top of memory reported to the operating system is hi gher than the top of memory programmed in the piix/piix3 top of memory register), the bios should not enable type f for any channel. 2. for the piix in external dma mode (selected via a strapping option on the tc signal), the piix tri-states the aen, tc, and dack[7:5, 3:0]# signals, and also forwards pci master i/o accesses to location 0000h to isa. 3.4.1. type f timing type f cycles occur back to back at a minimum r epetition rate of 3 sysclks. the type f cycles are always performed using the 4 byte dma buffer. type f transfers and the use of the dma buffer are invoked in the mbdmax register. the 4 byte buffer and the type f timings may be used only when the dma channel is programmed to increment mode (not decrement), and cannot be used when the channel is programmed to operate in block mode (single transfer mode and demand mode are legal). in addition, verify transfers are not supported with type f dma. the piix device does not support type fdma write timings on dma channels, only at compatible mode timings should be used for writes. type fdma read timings on dma channels are supported by the piix. 3.4.2. isa refresh cycles refresh cycle r equests are generated by two sources the refresh controller inside the piix/piix3 component or isa bus masters other than the piix. in both cases, the piix/piix3 generates the isa memory refresh. the piix/piix3 enables address lines sa[7:0]. thus, when memr# goes active, the entire isa system memory is refres hed at one time. memory slaves on the isa bus must not drive any data onto the data bus during the refresh cycle. the piix/piix3 maintains a four deep buffer to record internally generated refresh requests that have not been serviced. counter 1 in the timer register set should be programmed to provide a request for refresh about every 15s. initiated refresh cycle the piix/piix3 asserts refresh# to indicate a refresh cycle and then drives the address lines sa[7:0] onto the isa bus and generates memr# and smemr#. the piix/piix3 drives aen and bale high for the entire refresh cycle. the memory device may extend this refresh cycle by pulling iochrdy low. isa bus refresh cycles are completely dec oupled from dram refresh. transactions driven by pci masters that target isa or ide resources while refresh is active are held off with wait states until the refresh is complete. isa master initiated refresh cycle if an isa bus master holds the isa bus longer than 15 sec, the isa master must initiate memory refresh cycles. if the isa bus master initiates a refresh cycle before it reli nquishes the bus, it floats the address lines and control signals and asserts the refresh# to the piix. the piix/piix3 drives address lines sa[7:0] and memr# onto the isa bus. bale is driven high and aen is driven low for the entire refresh cycle. if the isa bus master holding the bus does not a generate a refresh request and the piix's internal refresh request is not serviced within the normal 15 m s, a refresh queue counter is incremented. the counter records up to four incomplete refresh cycles, which are all executed as soon as piix/piix3 gets the isa bus.
e 82371fb (piix) and 82371sb (piix3) 95 3.5. pci local bus ide the piix/piix3 integrates a high performance interface from pci to ide. this interface is capable of accelerated pio data transfers as well as acting as a pci bus master on behalf of an ide dma slave device. the piix/piix3 provides an interface for both primary and secondary ide connectors (figure 3). the ide data transfer command strobes, dma request and grant signals, and iordy signal interface directly to the piix. the ide data lines interface directly to the piix, and are buffered to provide part of the isa address bus as well as the x-bus chip select signals. the ide address and chip select signals are multiplexed onto the la[23:17] lines. the ide connector signals are driven from the la[23:17] lines by an als244 buffer. only pci masters have access to the ide port. isa bus masters cannot access the ide i/o port addresses. memory targeted by the ide interface acting as a pci bus master on behalf of ide dma slaves must reside on pci, usually main memory implemented by the host-to-pci bridge. als245 soe# sdir la[23:17] sa[19:8] sbhe# pcs# apiccs# isa bus signals als245 dd[15:0] primary ide connector secondary ide connector iordy dior# diow# ddrq0 ddack0# ddrq1 ddack1# 051903_3.drw piix/piix3 da[2:0] da[2:0] cs1s# cs3s# cs1p# cs3p# soe# 74als00 soe# sdir la[23]/ cs1s la[22]/ cs3s la[21]/ cs1p la[20]/ cs3p 051903 notes: support for older drives: there are cases where the piix/piix3 asserts both ide chip selects (cs1x and cs3x). some older drives may not operate properly when both chip selects are asserted. because the ide chip selects are muxed with the isa la lines, the 74als00 in the figure is used to ensure proper operation of older drives by gating the la signals with soe#. figure 3. piix/piix3 ide interface
82371fb (piix) and 82371sb (piix3) e 96 two connectors (primary and secondary) and two drives per connector (master and slave) are supported as shown in figure 4. piix/piix3 ideconn.drw master (drive 0) slave (drive 1) primary connector (p) master (drive 0) slave (drive 1) secondary connector (s) ideconn figure 4. ide connector and drive nomenclature 3.5.1. ata register block decode the ide ata i/o ports are decoded by the piix/piix3 when enabled in the pcicmd and idetim registers for function 1. (ata stands for "at attachment" the specification for at compatible drive interfaces). the actual ata registers are implemented in the drive itself. an access to the ide registers results in the assertion of the appropriate chip select for the register. the transaction is then run using compatible timing and using the ide command strobes (dior#, diow#). for each cable (primary and secondary), there are two i/o ranges; the command block that corresponds to the cs1x# chip select, and the control block that corresponds to the cs3x# chip select. the command block is an 8 byte range while the control block is a 4 byte range. the upper 16 bits of the i/o address are decoded as all 0s. primary command block offset: 01f0h primary control block offset: 03f4h secondary command block offset: 0170h secondary control block offset: 0374h table 13 specifies the registers as they affect the piix/piix3 hardware definition.
e 82371fb (piix) and 82371sb (piix3) 97 table 13. ide legacy i/o port definition: command block (cs1x# chip select) io offset register function (read / write) access 00h data r/w 01h error/features r/w 02h sector count r/w 03h sector number r/w 04h cylinder low r/w 05h cylinder high r/w 06h drive/head r/w 07h status/command r/w the data register is accessed as a 16-bit register for pio transfers (except for ecc bytes). all other registers are accessed as 8-bit quantities. table 14. ide legacy i/o port definition: control block (cs3x# chip select) io offset register function (read / write) access 00h reserved reserved 01h reserved reserved 02h alt status/device control r/w 03h forward to isa (floppy) r/w the piix/piix3 claims all accesses to these ranges. the byte enables do not have to be externally decoded to assert devsel#. accesses to byte 3 of the control block are forwarded to isa where the floppy disk controller responds. each of the two drives (drive 0 or 1) on a cable implement separate ata register files. to determine the targeted drive, the piix/piix3 shadows the value of bit 4 (drive bit) of byte 6 (drive/head register) of the ata command block (cs1x#) for each of the two ide connectors (primary and secondary). 3.5.2. enhanced timing modes the piix/piix3 includes fast timing modes. the fast timing modes can be enabled only for the ide data ports. all other transactions to the ide registers are run in single transaction mode with compatible timings. up to 2 ide devices may be attached per ide connector (drive 0 and drive 1). for each connector in a piix system, only one fast timing mode may be specified (via the idetim register). this mode can be applied to drive 0, drive 1, or both. transactions targeting the other drive will use compatible timing. for the piix3, the idetim and sidetim registers permit different timing modes to be programmed for drive 0 and drive 1 of the same connector.
82371fb (piix) and 82371sb (piix3) e 98 3.5.2.1. back-to-back pio ide transactions ide data port transaction latency consists of startup latency, cycle latency, and shutdown latency. cycle latency consists of the i/o strobe assertion length and recovery time. recovery time is provided so that transactions may occur back-to-back on the ide interface (without incurring startup and shutdown latency) without violating minimum cycle periods for the ide interface. startup latency is incurred when a pci master cycle targeting the ide data port is dec oded and the da[2:0] and csxx# lines are not set up. startup latency provides the setup time for the da[2:0] and csxx# lines with respect to the read and write strobes (dior# and diow#). shutdown latency is incurred after outstanding scheduled ide data port transactions (either a non-empty write post buffer or an outstanding read prefetch cycles) have completed and before other transactions can proceed. it provides hold time on the da[2:0] and csxx# lines with respect to the read and write strobes (dior# and diow#). cycle latency is the latency incurred by each individual 16-bit ide data port transfer, and consists of command strobe width and recovery time. the command strobe assertion width is selected by the idetim register and may be set to 2, 3, 4, or 5 pci clo cks. the recovery time is selected by the idetim register and may be set to 1, 2, 3, or 4 pci clocks. for the piix3, the master drive (drive 1) and slave drive (drive 0) can be programmed to different command strobe assertion widths and recovery times via the idetim and sidetim registers. if iordy is asserted when the initial sample point is reached, no wait states are added. if iordy is negated when the initial sample point is reached, additional wait states are added. since the rising edge of iordy must be synchronized, at least two additional pci clocks are added. note bit 2 (16-bit i/o recovery enable) of the isa controller recovery timer register does not add wait states to ide data port read accesses when any of the fast timing modes are enabled. 3.5.2.2. iordy masking the iordy signal can be forced asserted on a drive by drive basis via the idetim register. 3.5.2.3. pio 32 bit ide data port mode if the 32-bit ide data port mode is enabled (via bit 4 and 0 of the idetim register), 32-bit accesses to the ide data port address (default 01f0h primary, etc.) result in two back to back 16-bit transactions to idethe 32-bit data port feature is enabled for all timings, not just enhanced timing. 3.5.3. bus master function the piix/piix3 can act as a pci bus master on behalf of an ide slave device. two pci bus master channels are provided one channel for each ide connector (primary and secondary). by performing the ide data transfer as a pci bus master, the piix/piix3 off-loads the cpu and improves system performance in multitasking environments. physical region descriptor format the physical memory region to be transferred is described by a physical region descriptor (prd). the prds are stored in a table in memory. the data transfer proceeds until all regions described by the prds in the table have been transferred. note that the bus master ide does not support memory for regions or prds on isa.
e 82371fb (piix) and 82371sb (piix3) 99 each prd entry is 8 bytes in length. prds must be aligned on 64-kbyte boundaries. the first 4 bytes specify the byte address of a physical memory region. the next two bytes specify the count of the region in bytes (64-kbyte limit per region). a value of zero in these two bytes indicates 64 kbytes. bit 7 of the last byte indicates the end of the table (eot). bus master operation terminates when the last descriptor has been retired. 051910_3.drw byte 3 byte 2 byte 1 byte 0 eot reserved byte count [15:1] memory region physical base address [31:1] memory region main memory 0 0 051910 figure 5. physical region descriptor table entry note the memory region specified by the descriptor cannot straddle a 64-kbyte boundary. this means that the byte count can be limited to 64 kbytes and the incrementer for the current address register need only extend from bit 1 to bit 15. also, the total sum of the descriptor byte counts must be equal to or greater than the size of the disk transfer request. if greater than the disk transfer request, the driver must terminate the bus master transaction (by setting bit 0 in the bus master ide command register to 0) when the drive issues an interrupt to signal transfer completion. operation to initiate a bus master transfer between memory and an ide dma slave device, the following steps are required: 1. software prepares a prd table in main memory. each prd is 8 bytes long and consists of an address pointer to the starting address and the transfer count of the memory buffer to be transferred. in any given prd table, two consecutive prds are offset by 8-bytes and are aligned on a 4-byte boundary. 2. software provides the starting address of the prd table by loading the prd table pointer register . the direction of the data transfer is specified by setting the read/write control bit. clear the interrupt bit and error bit in the status register. 3. software issues the appropriate dma transfer command to the disk device. 4. engage the bus master function by writing a 1 to the start bit in the bus master ide command register for the appropriate channel. the first entry in the prd table is fetched by the piix. the channel remains masked until the first descriptor is loaded. 5. the controller transfers data to/from memory responding to dma requests from the ide device. 6. at the end of the transfer, the ide device signals an interrupt. 7. in response to the interrupt, software resets the start/stop bit in the command register. it then reads the controller status and then the drive status to determine if the transfer completed successfully.
82371fb (piix) and 82371sb (piix3) e 100 note that the irq14 signal must be used to signal interrupts for the primary channel in bus master mode; mirq0 must be used for the secondary channel. when the last data transfer for a region has been completed on the ide interface, the next descriptor is fetched from the table. the descriptor contents are loaded into the current base and current count registers. the last prd in a table has the end of list (eol) bit set. the pci bus master data transfers terminates when the physical region described by the last prd in the table has been completely transferred. the active bit in the bmisx register is set to 0 and the ddrqx signal is masked. line buffer a single line buffer exists for the pci bus master ide interface. this buffer is not shared with any other function. the buffer is maintained in either the read state or the write state. writes are always 4-dword bursts and invalid dwords have c/be[3:0]#=f. the size of the buffer is 32 bytes, and is aligned on the cache line boundary. the line buffer allows burst data transfers to proceed at peak transfer rates. 3.6. universal serial bus host controller (piix3 only) piix3 contains a usb host controller (hc). the host controller includes the root hub with two usb ports. this permits connection of two usb peripheral devices directly to the piix3 without an external hub. if more devices are required, an external hub can be connected to either of the built-in ports. the usbs pci configuration registers are located in function 2, pci configuration space. the piix3 host controller completely supports the standard universal host controller interface (uhci) and thus, takes advantage of the standard software drivers written to be compatible with uhci. figure 6 shows a conceptual view of a usb system. uhci consists of two parts ? host controller driver (hcd) and host controller (hc). the host controller interfaces to the usb system software in the host via the hcd. the hcd software manages the host controller operation and is responsible for scheduling the traffic on usb by posting and maintaining transactions in system memory. hcd is part of the system software and is typically provided by the operating system v endor. hcd provides the software layer between the piix3s host controller and the usbd software layer (also located in the operating system). the uhcis hcd software interprets requests from the usbd and builds frame list, transfer descriptor, queue head, and data buffer data structures for the host controller. the data structures are built in system memory and contain all necessary information to provide end-to-end communication between client software in the host and devices on the usb. the piix3s host controller moves data between system memory and devices on the usb by processing these data structures and generating the transaction on usb. the host controller executes the schedule lists generated by hcd and reports the status of transactions on the usb to hcd. command execution includes generating serial bus token and/or data packets based on the command and initiating transmission on usb. for commands that require the host controller to receive data from the usb device, the host controller receives the data and then transfers it to the system memory pointed to by the comm and. the uhcis hcd provides sufficient commands and data to keep ahead of the host controller execution and analyzes the results as the commands are completed. the piix3 provides support for usb keyboard and mouse operation with an operating system environment which does not have the complete usb software drivers loaded. this allows application programs which directly access system i/o space to function with a usb key board or mouse. the usb system will emulate a 8042 based keyboard controller. the piix3 has five controller issues regarding usb transactions, each of which is described below. multiple usb babble interrupts may be observed. if a babble occurs in a frame, a hardware interrupt will be generated at the end of the frame. additionally, the interrupt will occur in empty frames which immediately follow the frame in which the babble occurred and also in the first non-empty frame. an empty frame is defined as one with no active transfer descriptors (tds). this means extra hardware interrupts can be generated to the system. these interrupts are treated as spurious interrupts by the hcd interrupt handler.
e 82371fb (piix) and 82371sb (piix3) 101 a low speed length babble occurring in a frame followed by a subsequent clearing of the run/stop bit will cause the host controller to lock up from which it can only be restarted by a hardware reset. a length babble occurs when a device transmits more than the maximum number of bits as specified in the transfer descriptor. an eof babble occurs when a device transmits past the frame eof time point. this condition does not exist if an eof babble occurs. if this occurs, the usb host controller can not be restarted, disabling the system from performing any further usb transactions. a software workar ound can prevent a length babble from being recognized by the host controller for low speed transactions. the software will then be responsible for detecting the occurrence of a low speed length babble. the host controller detection of low speed length babble is prevented by setting the max packet length field in each low speed transfer descriptor to a value greater than the actual number of low speed bytes that can be sent in a frame (approximately 200). the software will detect the babble by comparing the actual length recorded in the transfer descriptor with a value representing the true max packet length for the endpoint. low speed length babble will cause usb port disable. if a low speed length babble (see description above) occurs in a frame, the root hub through which it is attached will be disabled. this is a normal condition for a babble which exceeds past the eof point, but is an incorrect condition for length babbles occurring within a frame. this means the usb port which is disabled will not receive subsequent packets until the port is reenabled by software. this condition can be corrected using the procedure described above. a bit stuff error occurs on a usb transaction transferring data from the usb device to the piix3. the bit stuff occurs, but with wrong data value (extra stuff bit was a 1 instead of 0). the data and crc value are transferred correctly with no errors. the piix3 will detect the bit stuff error, discard the data, clear the active bit, and set the bit stuff error bit. the piix3 will incorrectly acknowledge (ack) the transfer to the usb device, will not update the queue header, and does not set the stall bit. this condition can occur if the usb device inserts the wrong stuff bit or if noise on the usb sub system causes only this single bit to c hange. this means the usb devices data toggle bit will become out of sync with the host schedules data toggle bit. this will effectively result in a stalled usb device endpoint, halting data transfers to or from the usb device. the usb host controller software (uhci drivers) must check for a set bit stuff error bit with no corresponding stall bit set or simply check for an inactive transfer descriptor with a non-zero status field. when this condition is detected, the usb host controller software must stall the device endpoint and reinitialize the usb device. if pci latency at the end of a usb transaction pushes the status update beyond the start of the next frame, then the babble, nak, and timeout error condition detection may be delayed by one frame. there is no visual effect on functionality of performance. an alternative method of status monitoring in software is necessary for immediate detection. each of the 3 conditions can be detected as described below. 1. nak status: if the active bit is set then no patch is needed as the transaction will be automatically retried. 2. babble status: if error count <> 0, which precludes crc/timeout conditions and no other status bits are set other than the stalled bit, precluding bit stuff and data buffer conditions, then treat this babble condition like a stall. 3. timeout status: if the stalled bit is set and error count = 0 and either there is no data buffer error or there is no bitstuff error, then treat this condition as a crc/timeout error. more information concerning the piix3 usb host controller operation can be found in the universal host controller interface design guide, available from intel literature center as document number 297650.
82371fb (piix) and 82371sb (piix3) e 102 universal serial bus driver (usbd) universal host controller driver (hcd) piix3 universal host controller (hc) usb device usb usb_ blk. dr w hardware client software system software usb device usb universal host controller interface (uhci) usb_blk figure 6. usb system conceptual view 3.7. interval timer the piix/piix3 contains three counters that are equivalent to those found in the 82c54 programmable interval timer. the three counters are contained in one piix/piix3 timer unit, referred to as timer-1. each counter output provides a key system function. c ounter 0 is connected to interrupt controller irq0 and provides a system timer interrupt for a time-of-day, diskette time-out, or other system timing functions. counter 1 generates a refresh request signal and counter 2 generates the tone for the speaker. the 14.31818 mhz counters normally use osc as a clock source. counter 0, system timer this counter functions as the system timer by controlling the state of irq0 and is typically programmed for mode 3 operation. the counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. the counter loads the initial count value one counter period after software writes the count value to the counter i/o address. the counter initially asserts irq0 and decrements the count value by two each counter period. the counter negates irq0 when the count value reaches 0. it then reloads the initial count value and again decrements the initial count value by two each counter period. the counter then asserts irq0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting and negating irq0.
e 82371fb (piix) and 82371sb (piix3) 103 counter 1, refresh request signal this counter provides the refresh request signal and is typically programmed for mode 2 operation. the counter negates refresh request for one counter period (838 ns) during each count cycle. the initial c ount value is loaded one counter period after being written to the counter i/o address. the counter initially asserts refresh request, and negates it for 1 counter period when the count value reaches 1. the counter then asserts refresh request and continues counting from the initial count value. counter 2, speaker tone this counter provides the speaker tone and is typically programmed for mode 3 operation. the counter provides a speaker frequency equal to the counter clock frequency (1.193 mhz) divided by the initial count value. the speaker must be enabled by a write to port 061h. 3.8. interrupt controller the piix/piix3 provides an isa compatible interrupt controller that incorporates the functionality of two 82c59 interrupt controllers. the two controllers are cascaded so that 13 external and three internal interrupts are possible. the master interrupt controller provides irq [7:0] and the slave interrupt controller provides irq [15:8] (figure 7). the three internal interrupts are used for internal functions only and are not available to the user. irq2 is used to cascade the two controllers together. irq0 is used as a system timer interrupt and is tied to interval timer 1, counter 0. the mirq0/irq0 pin will function as the irq0 output and should be connected to the intin2 input of the ioapic when irq0 enable bit is set in the mirq0 register. irq13 is connected internally to ferr#. the remaining 13 interrupt lines (irq[15,14,12:3,1]) are available for external system interrupts. edge or level sense selection is programmable on an individual channel by channel basis. the interrupt unit also supports interrupt steering. the piix/piix3 can be programmed to allow the four pci active low interrupts (pirq[d:a]#) to be internally routed to one of 11 interrupts (irq[15,14,12:9,7:3]). in addition, the motherboard interrupts (mirq[1:0] for piix and mirq0 for piix3) may be routed to any of the 11 interrupts. the interrupt controller consists of two separate 82c59 cores. interrupt controller 1 (cntrl-1) and interrupt controller 2 (cntrl-2) are initialized separately and can be programmed to operate in different modes. the default settings are: 80x86 mode, edge sensitive (irq[15:0]) detection, normal eoi, non-buffered mode, special fully nested mode disabled, and cascade mode. cntrl-1 is connected as the master interrupt controller and cntrl-2 is connected as the slave interrupt controller. note that irq13 is generated internally (as part of the coprocessor error support) by the piix. irq12/m is generated internally (as part of the mouse support) when bit-4 in the xbcs register is set to a 1. when this bit is set to a 0, the standard irq12 function is provided and irq12 appears externally. intr (to cpu) 82c59 core controller 1 (master) timer 1 counter 0 irq1 irq3 irq4 irq5 irq6 irq7 051904_3.drw 0 1 2 3 4 5 6 7 82c59 core controller 2 (slave) irq9 irq11 irq12/mouse ferr# irq14 irq15 0# 1 2 3 4 5 6 7 intr irq8# irq10 051904 figure 7. block diagram of the interrupt controller
82371fb (piix) and 82371sb (piix3) e 104 3.8.1. programming the icws/ocws the interrupt controller accepts two types of command words generated by the cpu or bus master: 1. initialization command words (icws) : before normal operation can begin, each interrupt controller in the system must be initialized. in the 82c59, this is a two to four byte s equence. however, for the piix, each controller must be initialized with a four byte sequence. this four byte sequence is required to configure the interrupt controller correctly for the piix/piix3 implementation. this implementation is isa-compatible. the four initialization command words are referred to by their acronyms: icw1, icw2, icw3, and icw4. the base address for each interrupt controller is a fixed location in the i/o memory space, at 0020h for cntrl-1 and at 00a0h for cntrl-2. an i/o write to the cntrl-1 or cntrl-2 base address with data bit 4 equal to 1 is interpreted as icw1. for piix-based isa systems, three i/o writes to "base address + 1" (021h for cntrl-1 and 0a1h for cntrl-2) must follow the icw1. the first write to "base address + 1" (021h/0a1h) performs icw2, the second write performs icw3, and the third write performs icw4. 2. operation command words (ocws): these are the command words that dynamically reprogram the interrupt controller to operate in various interrupt modes. any interrupt lines can be masked by writing an ocw1. a 1 written in any bit of this command word ma sks incoming interrupt r equests on the corresponding irqx line. ocw2 is used to control the rotation of interrupt priorities when operating in the rotating priority mode and to control the end of interrupt (eoi) function of the controller. ocw3 set up reads of the isr and irr, enable/disables the special mask mode (smm), and sets up the interrupt controller in polled interrupt mode. the ocws can be written to the interrupt controller any time after initialization. 3.8.2. edge and level triggered mode in isa systems this m ode is programmed using bit 3 in icw1. with piix/piix3 this bit is disabled and a new register for edge and level triggered mode selection (per interrupt input) is included. this is the edge/level control registers elcr1 and elcr2. the default programming is equivalent to programming the ltim bit (icw1 bit 3) to a 0 (all interrupts selected for edge triggered mode). note, that irq0, 1, 2, 8#, and 13 can not be programmed for level sensitive mode and can not be modified by software. if an elcr bit = 0, an interrupt request is recognized by a low to high transition on the corresponding irqx input. the irq input can remain high without generating another interrupt. if an elcr bit = 1, an interrupt request is recognized by a high level on the corresponding irq input and there is no need for an edge detection. the interrupt request must be removed before the eoi command is issued to prevent a second interrupt from occurring. in both the edge and level triggered modes, the irq inputs must remain asserted until the cycle starts (pci inta cycle); with frame# and irdy# both asserted. after that, the irq may be removed. if the irq input goes inactive before this time, a default irq7 occurs when the cpu acknowledges the interrupt. this can be a useful safeguard for detecting interrupts caused by spurious noise glitches on the irq inputs. to implement this feature, the irq7 routine is used for "clean up" simply executing a return instruction, thus ignoring the interrupt. if irq7 is needed for other purposes, a default irq7 can still be detected by reading the isr. a normal irq7 interrupt sets the corresponding isr bit. a default irq7 does not set this bit. however, if a default irq7 routine occurs during a normal irq7 routine, the isr remains set. in this case, it is necessary to keep track of whether or not the irq7 routine was previously entered. if another irq7 occurs, it is a default. 3.8.3. interrupt steering the piix/piix3 can be programmed to allow four pci programmable interrupts (pirq[d:a]#) to be internally routed to one of 11 interrupts (irq[15,14,12:9,7:3]) using the pirqx route control register. pclk is used to synchronize the pirqx# inputs. the assignment is programmable through the pirqx route control
e 82371fb (piix) and 82371sb (piix3) 105 registers. one or more pirqx# lines can be routed to the same irqx input. if interrupt steering is not required, the route registers can be programmed to disable steering. for the piix3, the universal serial bus (usb) module interrupt is hardwired to the pirqd# signal. when the usb is enabled, the usb host controller in piix3 uses the pirqd# input to the internal interrupt controller. if an ioapic is used, the usb outputs interrupts on pirqd# to the external ioapic. when the usb function is disabled, other pci devices can use the pirqd# input. the pirqx# lines are defined as active low, level sensitive to allow multiple interrupts on a pci board to share a single line across the connector. when a pirqx# is routed to a specified irq line, the software must change the irq's corresponding elcr bit to level sensitive mode. note, that this means that the selected irq can no longer be used by an isa device, unless that isa device can respond as an active low level sensitive interrupt. the 82371fb piix supports up to two programmable interrupts (mirq[1:0]; intended for use with motherboard devices) to be routed to one of the 11 interupts (irq[15,14,12:9,7:3]) using the mbirqx route control register. the routing is accomplished in the same manner as for the pirqx# inputs, except that the interrupts are active high. two mirqx lines may be routed to the same irqx input. if interrupt steering is not required, the mbirqx registers can be programmed to disable routing. note that only one motherboard interrupt (mirq0) is available on piix3. for the 82371fb piix , when more than one mirq line is routed to an irq input, the software must change the irq's corresponding elcr bit to level sensitive mode. interrupt sharing for motherboard devices must be evaluated for the particular combination of devices under consideration. the irq selected bit mbirqx[3:0] can no longer be used by an isa device, unless that isa device can respond as an active high level sensitive interrupt. irq[15:9,8#,7:1] pirq[a:c]# mirq0 051909_3.drw to internal 82c59s piix/piix3 interrupt steering logic mirq1 (piix only) (piix and piix3) pirqd# universal serial bus module (piix3 only) interrupt 051909 note: mirq1 is only availabe on piix. mirq0 is available on both piix and piix3. figure 8. interrupt steering 3.9. stand-alone ioapic support (piix3) the piix3 supports a stand-alone ioapic device on the isa x-bus. the piix3 provides a chip select signal (apiccs#) for the ioapic. it also provides handshake signals to maintain buffer coherency in the ioapic environment.
82371fb (piix) and 82371sb (piix3) e 106 apiccs# is generated when the pci memory cycle address matches the apics programmed address and the apiccs# function is enabled in the xbcs register. the apic address can be relocated by programming the apic base address register (apicbase). apiccs# is only generated for pci originated cycles and is not generated for isa originated cycles. this pci cycle is forwar ded to the isa bus. to avoid address aliasing conflicts with other isa devices, piix3 drives sa[19:16] and la[23:17] to 0 and drives sa[15:0] corresponding to pci ad[15:2] and c/be[3:0]#. when the apiccs# function is enabled, the xoe#/xdir# signals controlling the x-bus tranceiver and the soe#/sdir signals controlling the ide dd isolation transceiver are also enabled during accesses to the ioapic. the ioapic signals (apiccs#, apicreq#, and apicack#) are multiplexed with dd14, testin#, and pcirst#, respectively. figure 9 shows how these signals are connected in systems with and without the ioapic device. the internal irq0 signal can be routed to the external pin mirq0 using bit 5 in the mbirq route control register 0. this changes mirq0 to an output signal and allows the irq0 signal to be connected to the external io-apic. the secondary ide device interrupt should then be routed to irq15. piix3 dd14/apiccs# testin#/apicreq# picrst#/apicack# i/o apic cs# apicreq# apicack# rstdrv pcirst# rstdrv piix3 dd14/apiccs# testin#/apicreq# picrst#/apicack# rstdrv testin# pcirst# no connect rstdrv piix3 with i/o apic piix3 without i/o apic apic_sys.drw apic_sys figure 9. apic signal connections 3.10. intr signaling with pentium? processor local apic in virtual wire mode the pentium? processor with a local apic enabled in virtual wire (also called through local) mode requires a minimum deassertion time on the intr signal. the piix3 asserts intr asynchronously in a method compatible with the 8259a programmable interrupt controller, which does not guarantee this minimum deassertion time. this only affects pentium? processors which have a local apic and the local apic is in virtual wire mode of operation. this results in the following system impacts: pentium? uni-processor system with no io-apic: no impact since the pentium processor local apic must be placed in bypass mode of operation. this includes 430vx systems with piix3 and 430hx systems with piix3 but no io-apic.
e 82371fb (piix) and 82371sb (piix3) 107 pentium? uni-processor or dual processor with io-apic: affects systems which use local apic in virtual wire mode of operation. this can include intel 430hx pciset based systems with piix3 and an io-apic. see recommendations below. pentium? pro (uni-processor or dual processor): no impact as the pentium? pro processor intr signal does not require an intr deassertion. this includes intel 440fx pciset based systems with piix3. the system bios should incorporate one of the following recommendations: 1. in dual processor systems with only a single processor installed, the local apic s hould be disabled (placed in bypass or masked mode). if a second processor is later installed, the multiprocessing operating system may need to be reinstalled. 2. to overcome the minimum deassertion requirement in dual processor systems with both processors installed, set the pentium? processor register tr12 bit 14 to 1. this solution should be used in systems whose software uses interrupt gate or task gate interrupt handling. this solution should not be used if the system has software with uses trap gate interrupt handling latency times. 3. in dual processor systems with both processors installed, the io-apic can be placed into virtual wire model of operation via the io-apic. this solution can result in increased system interrupt handling latency times. 3.11. x-bus peripheral support the piix/piix3 provides positive decode (chip selects) and x-bus buffer control (xdir# and xoe#) for a real time clock, keyboard controller and bios for pci and isa initiated cycles. the piix/piix3 also generates rtcale (address latch enable) for the rtc. the chip selects are generated combinatorially from the isa sa(16:0) and la (23:17) address lines (note that it is assumed that isa masters drive sa(19:16) and la(23:17) low when accessing i/o devices). the piix/piix3 also provides ps/2 mouse support via the irq12/m signal and coprocessor functions (ferr# and ignne#). the chip selects and x-bus buffer control lines can be enabled/disabled via the xbcs register. coprocessor error function this function provides coprocessor error support for the cpu and is enabled via the xbcs register. ferr# is tied directly to the coprocessor error signal of the cpu. if ferr# is driven active to the piix, an internal irq13 is generated and an the intr output from the piix/piix3 is driven active. when a write to i/o location f0h is detected, the piix/piix3 negates irq13 (internal to the piix) and drives ignne# active. ignne# remains active until ferr# is driven inactive. note, that ignne# is not driven active unless ferr# is active. mouse function when the mouse interrupt function is enabled (via the xbcs register), the mouse interrupt function is provided on the irq12/m input signal. in this mode, a mouse interrupt generates an interrupt through irq12 to the host cpu. the piix/piix3 informs the cpu of this interrupt via a intr. a read of 60h releases irq12. if the mouse interrupt function is disabled, a read of address 60h has no effect on irq12/m. reads and writes to this register flow through to the isa bus. for additional information, see the irq12/m description in the signal description.
82371fb (piix) and 82371sb (piix3) e 108 3.12. power management the piix/piix3 has extensive power management capability permitting a system to operate in a low power state without being powered down. in a typical desktop personal computer there are two states power on and power-off. leaving a system powered on w hen not in use wastes power. the piix/piix3 provides a fast on/off feature that creates a third state called fast off (figure 10). when in the fast off state, the system consumes less power than the power-on state. the piix's power management architecture is based on three functionssystem management mode (smm), clock control, and advanced power management (apm). software (called smm code) controls the transitions between the power on state and the fast off state. the piix/piix3 invokes this software by generating an smi to the cpu (asserting the smi# signal). a variety of programmable events are provided that can generate an smi. the smm code places the system in either the power on state or the fast off state. a fast on event is an event that instructs the computer (via an smi to the cpu) to enter the power-on state in anticipation of system activity by the user. fast on events are programmable and include moving the mouse, pressing a key on the keyboard, an external hardware event, an incoming call to a system fax/modem, a rtc alarm, or the operating system. fast off power switch turned on fast off event (timer expires, extsmi#, rtc alarm, apm call) power switch turned off fast on event (mouse, keyboard, comport activity, extsmi#, rtc alarm, apm call) power switch turned off power on power off 051905_3.drw 051905 figure 10. fast on/off flow
e 82371fb (piix) and 82371sb (piix3) 109 3.12.1. smm mode smm mode is invoked by asserting the smi# signal to the cpu. the piix/piix3 provides a variety of programmable events that can generate an smi. when the cpu receives an smi, it enters smm mode and executes smm code out of smram. depending on the current state, the smm code places the system in either the power on state or the fast off state. in the power on state, the computer system operates normally. in this state one of the four programmable events listed below can trigger an smi. 1. a global idle timer called the fast off timer expires (an indication that the end user has not used the computer for a programmed period of time). 2. the extsmi# pin is asserted. 3. the operating system issues an apm call. 3.12.2. smi sources the smi# signal can be asserted by hardware interrupt events, the fast off timer, an external smi event (extsmi#), and software events (via the apmc and apms registers). enable/disable bits (in the smien register) permit each event to be individually masked from generating an smi. in addition, the smi# signal can be globally enabled/disabled in the smicntl register. status of the individual events causing an smi is provided in the smireq register. for detailed information on the smi control/status registers, refer to the register description section. hardware interrupt events hardware events (irq[12,8#,4,3,1] and the fast off timer) are enabled/disabled from generating an smi in the smien register. when enabled, the occurrence of the corresponding hardware event generates an smi (asserts the smi# signal), regardless of the current power state of the system. fast off timer the fast off timer is used to indicate (through an smi) that the system has been idle for a programmed period of time. the timer counts down from a programmed start value and when the count reaches 00h, can generate an smi. the timer decrement rate is programmable (via the smicntl register) and is re-loaded each time a system event occurs. this c ounter should not be programmed to 00h. system and break events are described in the see register. extsmi# the extsmi# input pin provides the system desi gner the capability to invoke smm with external hardware. for example, the extsmi# input could be connected to a "green button" permitting the user to enter the fast off state by depressing a button. the extsmi# generation of an smi is enabled/disabled in the smien register. for the piix3, the extsmi# signal can be used to provide a special protocol between the host-to-pci bridge and the piix3 (see mstat register description, 6b-6ah, function 0). software events software events (accessing the apmx registers) indicate that the os is passing power management information to the smi handler. there are two advanced power management (apm) registers apm control (apmc) and apm status (apms) registers. these registers permit software to generate an smi; by writing to the apmc register. for example, the apmc can be used to pass an apm command between apm os and bios and the apms register could be used to pass data between the os and the smi handler.
82371fb (piix) and 82371sb (piix3) e 110 the two apm registers are located in normal i/o space. the piix/piix3 subtractively decodes pci accesses to these registers and forwards the accesses to the isa bus. the apm registers are not accessible by isa masters. note that the remaining power management registers are located in pci configuration space. 3.12.3. clock control the cpu can be put in a low power state by asserting the stpclk# signal. stpclk# is an interrupt to the cpu. however, for this type of interrupt, the cpu does not generate an interrupt acknowledge cycle. once the stpclk# interrupt is executed, the cpu enters the stop grant state. in this state, the cpu's internal clocks are disabled and instruction execution is stopped. the stop grant state is exited when the stpclk# signal is negated. software can assert stpclk#, if enabled via the smicntl register, by a read of the apmc register. note that stpclk# can also be periodically asserted by using clock scaling as described below. the piix/piix3 automatically negates stpclk# when a break event occurs (if enabled in the see register). software can negate stpclk# by disabling stpclk# in the smicntl register or by a write to the apmc register. clock scaling (emulating clock division) clock scaling permits the piix/piix3 to periodically place the cpu in a low power state. this emulates clock division. when clock scaling is enabled, the cpu runs at full frequency for a pre-defined time period and then is stopped for a pre-defined time period. the run/stop time interval ratio emulates the clock division effect from a power/performance point of view. however, clock scaling is more effective than dividing the cpu frequency. for example, if the cpu is in the stop grant state and a break event occurs, the cpu clock returns to full frequency. in addition, there is no recovery time latency to start the clock. two programmable 8-bit clock scale timer control registers set the stpclk# high (negate) and low (assert) times the ctltmrh and ctltmrl registers. the timer is clocked by a 32 usec internal clock. this allows a programmable timer interval for both the stpclk# high and low times of 0-8 msec. 3.13. reset support the piix/piix3 integrates the system reset logic for the system. the piix/piix3 generates cpurst, pcirst#, and rstdrv during power up (pwrok) and when a hard reset is initiated through the rc register. for the piix3, the pcirst# signal is multiplexed with apicack#. when an external ioapic is used, the pcirst# functionality is provided by externally inverting the rstdrv signal (see stand-alone ioapic support section). the following piix/piix3 signals interface directly to the processor: - cpurst - intr - nmi - ignne# - smi# - stpclk# these signals are open drain. thus, external logic is not required for interfacing with the processors based on 3.3v technology which do no support 5v tolerant input buffers. during power-up these signals are driven low to prevent problems associated with 5v/3.3v power sequencing.
e 82371fb (piix) and 82371sb (piix3) 111 some pci devices may drive 3.3v friendly signals directly to 3.3v devices that are not 5v tolerant. if such signals are powered from the 5v supply they must be driven low when pcirst# is asserted. some of these signals may need to be driven high before cpurst is negated. pcirst# is negated 1 ms to 2 ms before cpurst to allow time for this to occur. 3.13.1. hardware strapping options for the piix/piix3, the sysclk signal is used during a hard reset to select the isa clock divisor (sampled high for divisor of 3 C 25 mhz pci operation. sampled low for a divisor of 4 C 33 mhz or 30 mhz pci operation). a 10k ohm resistor, jumperable as a pull up or pull down, on sysclk, can be used to configure divide-by-3 or divide-by-4 sysclk frequency. the logic level sensed on sysclk at reset configures the frequency. an alternate solution is using an open drain buffer enabled only during reset to drive the appropriate level on sysclk. for the piix, a strapping option on the tc during a hard reset selects between isa dma mode and an external dma mode (sampled high for isa dma mode and low for external dma mode).
82371fb (piix) and 82371sb (piix3) e 112 4.0. pinout and package information 4.1. pinout 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 1 2 3 4 5 7 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 vcc vcc dd0/sa8 irq4 sa7 irq3 sa6 dack2# sa5 tc sa4 bale vss sa3 sa2 sa1 sa0 memcs16# la23/cs1s irq10 la22/cs3s irq11 la21/cs1p irq12 vcc vss la20/cs3p irq14 dack0# la17/da0 dreq0 memr# dack5# memw# sd8 dack6# sd9 dreq6 sd10 sd11 sd13 sd14 vcc vcc dr eq7 sd12 iocs16# irq15 la19/da2 la18/da1 dack7# dreq5 vss sd15 ddrq0 phlda# ddrq1 diow# dior# iordy ddak0# ddak1# spkr sdir soe# ferr# ignne# intr smi# stpclk# extsmi# pwrok cpurst pcirst# init vcc vss pciclk vss testin# nmi osc bioscs# rtccs# kbcs# xoe# xdir mdrq1 mdrq0 mdak1 mdak0 mirq1 mirq0 rtcale pirqa# pirqb# pirqd# sysclk idsel vss vss vss phold# vss vss serr# irq1 irq8# iochk# sd7 sd6 sd5 irq9 sd4 dreq2 sd3 sd2 zerows# sd1 sd0 iochrdy smemr# aen dack3# smemw# ior# iow# dreq3 vss vcc rstdrv dack1# dreq1 refresh# irq7 irq6 irq5 dd15/pcs# dd14 dd13 dd12/sbhe# dd11/sa19 dd10/sa18 dd9/sa17 vss dd8/sa16 dd7/sa15 dd6/sa14 dd5/sa13 dd4/sa12 dd3/sa11 dd2/sa10 dd1/sa9 vss vss pirqc# ad22 c/be3# ad25 vcc vcc ad31 ad30 ad29 ad28 ad27 ad26 ad24 ad23 vcc vss ad21 ad20 ad19 ad18 ad17 ad16 c/be2# frame# irdy# trdy# vss vcc devsel# stop# par c/be 1# ad15 ad14 ad13 ad12 ad11 ad10 ad9 vss vcc ad8 c/be0# ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 vcc vcc pix3_pin.drw piix3 pinout changes (from piix) 36 dd14/apiccs# 128 pcirst#/apicack# 130 vdd3 (3.3 volts) 134 testin#/apicreq# 142 usbp1+ 143 usbp1- 144 usbp0+ 145 usbp0- 146 usbclk piix pix3_pin figure 11. piix/piix3 pin assignment
e 82371fb (piix) and 82371sb (piix3) 113 table 15. alphabetical pin assignment name pin # type ad0 206 i/o ad1 205 i/o ad2 204 i/o ad4 202 i/o ad5 201 i/o ad6 200 i/o ad7 199 i/o ad8 197 i/o ad9 194 i/o ad10 193 i/o ad11 192 i/o ad12 191 i/o ad13 190 i/o ad14 189 i/o ad15 188 i/o ad16 177 i/o ad17 176 i/o ad18 175 i/o ad19 174 i/o ad20 173 i/o ad21 172 i/o ad22 171 i/o ad23 168 i/o ad24 166 i/o ad25 165 i/o ad26 164 i/o ad27 163 i/o ad28 162 i/o ad29 161 i/o ad3 203 i/o name pin # type ad30 160 i/o ad31 159 i/o aen 20 o bale 64 o bioscs# 137 o c/be0# 198 i/o c/be1# 187 i/o c/be2# 178 i/o c/be3# 167 i/o cpurst 127 o dack0# 85 o dack1# 29 o dack2# 60 o dack3# 21 o dack5# 89 o dack6# 93 o dack7# 97 o dd0/sa8 55 i/o dd1/sa9 50 i/o dd2/sa10 49 i/o dd3/sa11 48 i/o dd4/sa12 47 i/o dd5/sa13 46 i/o dd6/sa14 45 i/o dd7/sa15 44 i/o dd8/sa16 43 i/o dd9/sa17 41 i/o dd10/sa18 40 i/o dd11/sa19 39 i/o dd12/sbhe# 38 i/o
82371fb (piix) and 82371sb (piix3) e 114 name pin # type dd13 37 i/o dd14 (piix) dd14/apiccs# (piix3) 36 i/o dd15/pcs# 35 i/o ddak0# 115 o ddak1# 116 o ddrq0 108 i ddrq1 111 i devsel# 184 i/o dior# 113 o diow# 112 o dreq0 87 i dreq1 30 i dreq2 12 i dreq3 25 i dreq5 91 i dreq6 95 i dreq7 99 i extsmi# 125 i ferr# 120 i frame# 179 i/o idsel 154 i ignne# 121 o init 129 o intr 122 o iochk# 6 i iochrdy 18 i/o iocs16# 71 i ior# 23 i/o iordy 114 i iow# 24 i/o name pin # type irdy# 180 i/o irq1 4 i irq3 58 i irq4 56 i irq5 34 i irq6 33 i irq7 32 i irq8# 5 i irq9 10 i irq10 73 i irq11 75 i irq12 77 i irq14 83 i irq15 81 i kbcs# 139 o la17/da0 86 i/o la18/da1 84 i/o la19/da2 82 i/o la20/cs3p 80 i/o la21/cs1p 76 i/o la22/cs3s 74 i/o la23/cs1s 72 i/o mdak1 (piix) usbp0+(piix3) 144 o mdrq0 (piix) usbp1-(piix3) 143 i mdrq1 (piix) usbp1+(piix3) 142 i memcs16# 70 i/o memr# 88 i/o memw# 90 i/o midak0 (piix) usbp0-(piix3) 145 o
e 82371fb (piix) and 82371sb (piix3) 115 name pin # type mirq0/irq0 147 o mirq1 (piix) usbclk (piix3) 146 i/o nmi 135 o osc 136 i par 186 o pciclk 132 i pcirst# (piix) picrst#/ apicack# (piix3) 128 o phlda# 110 i phold# 109 o pirqa# (piix) pirqa# (piix3) 149 149 i i/o pirqb# 150 i pirqc# 151 i pirqd# 152 i pwrok 126 i refresh# 31 i/o rstdrv 28 o rtcale 148 o rtccs# 138 o sa0 69 i/o sa1 68 i/o sa2 67 i/o sa3 66 i/o sa4 63 i/o sa5 61 i/o sa6 59 i/o sa7 57 i/o sd0 17 i/o sd1 16 i/o name pin # type sd2 14 i/o sd3 13 i/o sd4 11 i/o sd5 9 i/o sd6 8 i/o sd7 7 i/o sd8 92 i/o sd9 94 i/o sd10 96 i/o sd11 98 i/o sd12 100 i/o sd13 101 i/o sd14 102 i/o sd15 107 i/o sdir 118 o serr# 3 i smemr# 19 o smemw# 22 o smi# 123 o soe# 119 o spkr 117 o stop# 185 i/o stpclk# 124 o sysclk 153 o tc 62 o testin# (piix) testin#/ apicreq# (piix3) 134 i trdy# 181 i/o vcc 27 v vcc 53 v
82371fb (piix) and 82371sb (piix3) e 116 name pin # type vcc 54 v vcc 78 v vcc 103 v vcc 104 v vcc (piix) vcc3 (piix3) 130 v vcc 157 v vcc 158 v vcc 169 v vcc 183 v vcc 196 v vcc 207 v vcc 208 v vss 1 v vss 2 v vss 26 v vss 42 v name pin # type vss 51 v vss 52 v vss 65 v vss 79 v vss 105 v vss 106 v vss 131 v vss 133 v vss 155 v vss 156 v vss 170 v vss 182 v vss 195 v xdir 141 i xoe# 140 o zerows# 15 i
e 82371fb (piix) and 82371sb (piix3) 117 4.2. package dimensions a d d1 l1 b units: mm 1 52 53 104 105 156 157 208 pkg_pix3.drw t a1 y * note* height measurements same as width measurements e1 c 051916 figure 12. 208 pin quad flat pack (qfp) dimensions table 16. 208 pin quad flat pack (qfp) dimensions symbol description value (mm) a seating height 4.25 (max) a1 stand-off 0.05 (min); 0.40 (max) b lead width 0.2 0.10 c lead thickness 0.15 +0.1/-0.05 d package length and width, including pins 30.6 0.4 d1 package length and width, excluding pins 28 0.2 e1 linear lead pitch 0.5 0.1 y lead coplanarity 0.08 (max) l1 foot length 0.5 0.2 t lead angle 0 o - 10 o
82371fb (piix) and 82371sb (piix3) e 118 5.0. testability (piix/piix3) 5.1. test mode description the test modes are decoded from the irq inputs (irq 7, 6, 5) and qualified with the testin# pin. test mode selection is asynchronous. these signals need to remain in their respective state for the duration of the test modes. the test modes are defined as follows. table 17. test modes test mode irq7 irq6 irq5 testin# nand tree 0 x x 0 nand tree x x 0 0 tri-state all outputs 1110 5.2. nand tree mode tri-states all outputs and bi-directional buffers except for xdir and dack1#. every output buffer except for xdir and dack1# is configured as an input in nand tree mode and included in the nand chain. the first input of the nand chain is mdrq1, and the nand chain is routed counter-clockwise around the chip (e.g., mdrq1, mdrq0, mdak1#, . . .). dack1# is an intermediate output, and xdir is the final output. pciclk and testin# are the only input pins not included in the nand chain. note in the table above there are two possible ways to select nand tree test mode. to perform a nand tree test, all pins included in the nand tree should be driven to 1 except for the following pins, which use inverting schmitt trigger inputs and should be driven to 0: table 18. perform nand tree test (pins driven to 0) pin # pin name 4 irq1 5 irq8# 6 iochk# 10 irq9 15 zerows# 32 irq7 33 irq6 34 irq5 56 irq4 58 irq3 73 irq10 75 irq11 77 irq12
e 82371fb (piix) and 82371sb (piix3) 119 table 18. perform nand tree test (pins driven to 0) pin # pin name 81 irq15 83 irq14 126 pwrok beginning with mdrq and working counter-clockwise around the chip, each pin can be toggled and a resulting toggle observed on dack1# or xdir. the dack1# output is provided so that the nand tree test can be divided into two sections. table 19. nand tree pin # pin name notes 134 testin# testin# should be driven to 0 for the duration of the nand tree test. 32 irq7 test mode select signal. 33 irq6 test mode select signal. 34 irq5 test mode select signal. 142 mdrq1 143 mdrq0 144 mdk1 145 mdk0 146 mirq1 147 mirq0 148 rtcale 149 pirqa# 150 pirqb# 151 pirqc# 152 pirqd# 153 sysclk 154 idsel 159 ad31 160 ad30 161 ad29 162 ad28 163 ad27 164 ad26 165 ad25 table 19. nand tree pin # pin name notes 166 ad24 167 c/be3# 168 ad23 171 ad22 172 ad21 173 ad20 174 ad19 175 ad18 176 ad17 177 ad16 178 c/be2# 179 frame# 180 irdy# 181 trdy# 184 devsel# 185 stop# 186 par 187 c/be1# 188 ad15 189 ad14 190 ad13 191 ad12 192 ad11 193 ad10 194 ad9 197 ad8
82371fb (piix) and 82371sb (piix3) e 120 table 19. nand tree pin # pin name notes 198 c/be0# 199 ad7 200 ad6 201 ad5 202 ad4 203 ad3 204 ad2 205 ad1 206 ad0 3 serr# 4 irq1 inverted input signal 5 irq8# inverted input signal 6 iochk# inverted input signal 10 irq9 inverted input signal 11 sd4 12 dreq2 13 sd3 14 sd2 15 zerows# inverted input signal 16 sd1 17 sd0 18 iochrdy 19 smemr# 20 aen 21 dack3# 22 smemw# 23 ior# 24 iow# 25 dreq3 28 rstdrv 29 dack1# intermediate nand-tree output. 30 dreq1 31 refresh# 32 irq7 inverted input signal table 19. nand tree pin # pin name notes 33 irq6 inverted input signal 34 irq5 inverted input signal 35 dd15 36 dd14 37 dd13 38 dd12 39 dd11 40 dd10 41 dd9 43 dd8 44 dd7 45 dd6 46 dd5 47 dd4 48 dd3 49 dd2 50 dd1 55 dd0 56 irq4 inverted input signal 57 sa7 58 irq3 inverted input signal 59 sa6 60 dack2# 61 sa5 62 tc 63 sa4 64 bale 66 sa3 67 sa2 68 sa1 69 sa0 70 memcs16# 71 iocs16# 72 la23 73 irq10 inverted input signal
e 82371fb (piix) and 82371sb (piix3) 121 table 19. nand tree pin # pin name notes 74 la22 75 irq11 inverted input signal 76 la21 77 irq12 inverted input signal 80 la20 81 irq15 inverted input signal 82 la19 83 irq14 inverted input signal 84 la18 85 dack0# 86 la17 87 dreq0 88 memr# 89 dack5# 90 memw# 91 dreq5 92 sd8 93 dack6# 94 sd9 95 dreq6 96 sd10 97 dack7# 98 sd11 99 dreq7 100 sd12 101 sd13 102 sd14 107 sd15 108 ddrq0 109 phold# 110 phlda# table 19. nand tree pin # pin name notes 111 ddrq1 112 diow# 113 dior# 114 iordy 115 ddak0# 116 ddak1# 117 spkr 118 sdir 119 soe# 120 ferr# 121 ignne# 122 intr 123 smi# 124 stpclk# 125 extsmi# 126 pwrok inverted input signal 127 cpurst# 128 pcirst# 129 init 132 pciclk input only, not included in the nand tree test mode. 135 nmi 136 osc 137 bioscs# 138 rtccs# 139 kbcs# 140 xoe# 141 xdir final nand tree output
82371fb (piix) and 82371sb (piix3) e 122 figure 13 is a schematic of the nand tree circuitry. mdrq1 mdrq0 rstdrv dreq1 kbccs# xoe# dack1# nand chain select dack1# xdir nand chain select xdir 051917_3.drw 051917 figure 13. nand tree circuitry nand tree timing requirements allow 500 ns for the input signals to propagate to the nand tree outputs (input-to-output propagation delay specification). 5.3. tri-state mode the testin# signal must be 0 and irqs 7, 6, and 5 must be 1 to enter the tri-state test mode. when in the tri-state test mode, all outputs and bi-directional pins are tri-stated, including the nand tree outputs.

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